Add a new option backend that uses values stored in CBFS files, similar
to the SeaBIOS runtime config options stored in files with the etc/
prefix. Options should be stored in CBFS with the option/ prefix. Values
can be set using `cbfstool coreboot.rom add-int -n option/<option-name>
-i <value>`. For simplicity, options should be stored in the COREBOOT
(RO) FMAP region, which is the default for cbfstool. This backend is not
available in SMM due to CBFS dependencies on vboot functions which are
not added to SMM, and thus the fallback will be returned by calls to
get_uint_option() in SMM.
Tested with QEMU Q35 by setting various options for "sata_mode" and
observing the console output for the SATA controller mode during
i82801ix_sata initialization.
Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
For edge trigger,the default is "rising edge"(invert=0),
and it needs to "invert" (invert=1) for falling edge.
BUG=b:359437265
TEST=emerge-brox coreboot chromeos-bootimage
oscilloscope measurement interrupt is triggered by falling edge
Change-Id: I132b43fd552d2babfbcd497bc6a017f354c69e10
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85966
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marx Wang <marx.wang@intel.corp-partner.google.com>
Change the maximum C state allowed when S0ix isn't used to C8
from C7S to solve the following error:
MWAIT C-state 0x33 not supported by HW (0x1010)
This is a result of copy-pasta from older SOCs, as C7 is not
supported on Alder Lake.
Tested on `starbook_adl` with Ubuntu 24.04 by booting, and
performing multiple S3 cycles.
Change-Id: Idb3e4d34361c8ac25ef144c0d1cda9f801ed0c54
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84622
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
If the modem is not completely disabled, it will cause issues with
suspend to RAM. Update the condition check in MD1_PWR_STA and increased
the MAX_RETRY_COUNT from 200 to 4000 to make sure that the modem has
sufficient time to completely disable before proceeding.
TEST=Measure the power and ensure that the DRAM enters self-refresh
mode.
BUG=b:377628718
Change-Id: I6e915d26e5b3caee36f4726bc2fc1c53cfc17bfc
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add eDP driver to adjust training flow and turn off PHY power before PHY
configuration to prevent potential link training failures.
DISP_DVO is a highly advanced variant of DP_INTF block for eDP or HDMI
or simply digital video output. DISP represents “display”, while DVO is
the abbreviation of “digital video output”. This version of DISP_DVO is
mainly designed for eDP1.5 protocol.
TEST=check edp training pass and show log:
EQ training pass
BUG=b:343351631
Change-Id: Iccba53f6c6181ca84624c216f9641a2ae9041671
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85949
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the initialization code for CPU Dynamic Voltage and Frequency
Scaling (DVFS) for MCUPM.
TEST=Build pass.
BUG=b:317009620
Change-Id: I92b7c57ad8c3d9e9954f02a08954939f45c5e2c2
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86041
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The if statement is repeated so merge it into one block.
Change-Id: I92f6d1b0a7fed4730f11e572b076f5dfdb91d96f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
As of commit a911b75848 ("mb/*: Remove old USB configurations from
SNB/bd82x6x boards") USB configurations are drawn exclusively from
devicetree. The old copy carried by early_init.c should have been
removed back then. Since it has nothing else, drop the whole file.
Remove xhci_overcurrent_mapping as it is now derived from
usb_port_config.
According to schematics only the first two ports are wired for xHCI
and both goes to OC0#. Remove OC pin assignment from disabled third
port so the (former) xhci_overcurrent_mapping can be derived
correctly. Also adjust xhci_switchable_ports and
superspeed_capable_ports to match.
Thanks to Patrick Rudolph for the information.
Change-Id: I6bdc9a188b2baa2207aaccb46821b58f97ff7da6
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
As of commit a911b75848 ("mb/*: Remove old USB configurations from
SNB/bd82x6x boards") USB configurations are drawn exclusively from
devicetree. These stuff should have been removed then.
Drop romstage.c from both variants that only carries the old USB
configurations and xhci_overcurrent_mapping devicetree setting that is
now derived from usb_port_config (they match).
Change-Id: I1a5d57ae9e3788e0c7788013c6fe387ec83efcf2
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85943
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
As xHCI ports 1-4 and OC pins 0-3 are all shared with EHCI,
xhci_overcurrent_mapping should never deviate from the USB 2 (EHCI)
overcurrent mapping specified in the USB port config in the devicetree.
Get the mapping from EHCI and free mainboards from specifying
it separately.
A Ghidra inspection of MRC binary indicates it is doing the same.
After this patch xhci_overcurrent_mapping becomes redundant and
will be removed in a follow-up.
Change-Id: Iab30a07c8df223e4053c5f28df5e5ed926f278f7
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Create the dirks variant of nissa reference board by copying the
template files to a new directory named for the variant.
The dirks variant is a twinlake platform.
BUG=b:389391653
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_DIRKS
Change-Id: I57ffb6025ee2115fa558668dc685a1970fc738d0
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85947
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Enable SaGv support for fatcat
BUG=None
BRANCH=None
TEST=Boot fatcat with SAGv enabled and verify in fsp debug logs
Change-Id: I340f4951fd33deadaac53edd30e2cf6bfc2a750b
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85272
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
As the mtk_pwrsel.{c,h} files are already under the soc/mediatek
directory, drop the file name prefix "mtk_" from them.
BUG=b:317009620
TEST=none
Change-Id: I28131d44067c33b5d8682a85cc8a73fc42604de3
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86059
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the Gerrit guidelines there is an old link pointing to the retired
coreboot wiki (https://www.coreboot.org/Git#Commit_messages) when the
commit message guidelines are referenced. Indeed this section was never
ported over to the new documentation and is missing.
This commit rewrites this guidelines and adds them as a new section
based on what was in the wiki and updates the link accordingly.
Change-Id: I1cd2b13da6fe59697d677c7350d73eda5d486544
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85915
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If no resource is found for a device, do not return directly, otherwise
the following code will no longer be executed.
Change-Id: Ida8019c383df4be2d37a1532a1759086e86124e6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85891
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Due to layout restrictions on mc_ehl2, the eMMC interface is limited to
operate in DDR50 mode. The alternative modes SDR104 and SDR50 are not
supported. Limit the capabilities in the eMMC controller to DDR50 mode
only so that the eMMC driver in OS will choose the right mode for
operation even if the attached eMMC card supports higher modes.
BUG=none
TEST=Boot into Linux and check dmesg output for mmc modes
Change-Id: I668bb5b0b3197497920b36bcf283c25d2a0c00ba
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85881
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The latest patch chain for mc_ehl5, commit 2d9a82cf8a
("mb/siemens/mc_ehl5: Rename SDIO converge layer register defines") and
following patches, have simplified the SD card code. This patch now
adapts the other mc_ehl mainboards accordingly to standardize the code.
Change-Id: Ieb2d540656408d2ce57a34e3e443b4273b9c48bb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85864
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since commit 64d9e85681
("cpu/x86/smm_module_hander: Set up a save state map"), the
smm_get_save_state() function can return a NULL pointer. Therefore, it
is crucial to ensure that code properly handles the potential for a
NULL pointer return value from smm_get_save_state().
Change-Id: Ie263393ca7d9d6b5e9868c5f73240fc788116cd0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The smm_get_save_state() function returns an invalid pointer (negative
pointer) when the cpu variable is equal to the number of CPUs. This
leads to a hang when the pointer is used to access the save state.
TEST=No unexpected hangs in System Management Mode (SMM) were detected
on fatcat.
Change-Id: I09f969105190a004372c43cb1542f5b716da1eda
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
EINT event mask register is used to mask EINT wakeup source. All wakeup
sources are masked by default. Since most MediaTek SoCs do not have this
design, we can't modify the kernel EINT upstream driver to solve the
issue "Can't wake using power button (cros_ec) or touchpad". So we add a
driver here to unmask all wakeup sources.
TEST=write eint data successfully.
BUG=b:317009620
Change-Id: I4bf3820a89172186b8f51591f8760787affbb7a3
Signed-off-by: Chhao Chang <ot_chhao.chang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84025
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
As of commit a911b75848 ("mb/*: Remove old USB configurations from
SNB/bd82x6x boards") USB configurations are drawn exclusively from
devicetree. These stuff should have been removed then.
Change-Id: I03b1bce9a12aa687a7c65db79efc2cddc1708a79
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
To ensure we find the correct firmware image, match against `$BOARD":`
rather than just `$BOARD`. This fixes an issue where another board (b1)
using the same firmware build or name as the one we are searching for,
causes the grep matching to return empty strings.
TEST=successfully extract the firmware image for CAREENA, which
previously failed.
Change-Id: I2f2a71f0b033938aafc1fd27e2996fe319614b3c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Commit fee8bcbcfb ("drivers/asmedia: Add code to enable AHCI for
ASM1061") renamed the ASMEDIA_ASPM_BLACKLIST Kconfig to ASMEDIA_ASM_1061
since the former was only ever used for that card.
However, commit fb24620534 ("mb/asrock: Add Z87 Extreme4 (Haswell)")
was merged first and used the old Kconfig, so the tree broke when the
AHCH patch was merged. Change the Kconfig to fix the tree.
Change-Id: If16455c43e583e7edbf7914db87346385d811190
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86056
Reviewed-by: Jan Philipp Groß <jeangrande@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The ASMedia ASM1061 seems to default to IDE mode, which seems to be the
source of payloads and Linux not recognizing/booting from drives
connected to it. From the behaviour of vendor firmware on the ASRock Z87
Extreme 4, the mode can be changed by setting the PCI Subclass register
to either 0x06 (SATA controller) or 0x01 (IDE controller). This register
seems to be read only, but can be unlocked for writing by setting bit 2
at offset 0xEC in the PCI config space.
Since the ASMEDIA_ASPM_BLACKLIST driver already existed and only matched
the ASM1061, rename it to ASMEDIA_ASM1061 and add the AHCI mode setting
code to it. To maintain consistency with chipset SATA ports, this is
also configurable through the existing sata_mode CMOS option with the
default set to AHCI.
Tested on the ASUS Maximus VI Gene.
Change-Id: I7a1470894261c7d14fadccdcade968f87f78fe23
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-by: Jan Philipp Groß <jeangrande@mailbox.org>
Enables onboard LEDs for power and reset button as well as flash chip
indicator LED. Also enables POST code display. Both LEDs and PCD turn
on when the system is powered and turn off once the payload is reached.
This mimics the behavior on vendor firmware.
Change-Id: I3fce671a292695bd14f1db16e2dc30c2cde0c1a7
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
List an additional USB debug port on one of the USB-2.0-Headers.
Change-Id: Ia2bfb8ff2fbfab426c569198466cc27b83a85bc7
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add various previously missing settings as well as a few devices,
also tidy up the comments and make whitespace consistent.
Tested on hardware, no regressions were observed.
Mainboard boots Arch Linux with EDKII payload, S3 suspend and
resume works, as before.
Change-Id: Ifbbb981cd62a49d112d2bc379f5941819ca70e44
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86006
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This port was done via autoport and subsequent manual tweaking.
Working:
- Haswell MRC.bin
- All four DDR3/DDR3L DIMM slots
- S3 suspend and resume
- D-Sub Port
- DVI-D Port
- HDMI Port
- RJ-45 Gigabit LAN Port
- All four rear USB 2.0 Ports
- All four rear USB 3.1 Gen1 Ports
- Both USB 2.0 headers
- USB 3.1 Gen1 header
- All six SATA3 6.0 Gb/s connectors by Intel
- Both PCI Express 3.0 x16 slots
- PCI Express 2.0 x16 slot
- PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter)
- HD Audio Jack (Audio output tested only)
- Front Audio Jack (Audio output tested only)
not (yet) tested:
- IR header
- COM Port header
- eSATA connector
- PS/2 Mouse/Keyboard Port
Change-Id: Icc2eb7430b77fe152cff1c90e80e6ba37cc903e1
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85884
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This port was done via autoport and subsequent manual tweaking.
The board features two socketed DIP-8 SPI flash chips, as well as a
BIOS selection via jumper and onboard Power and Reset switches.
Special thanks to Angel for enabling various LEDs/PCD functions!
Working:
- Haswell MRC.bin
- All four DDR3/DDR3L DIMM slots
- S3 suspend and resume
- HDMI-Out Port
- DVI-D Port
- RJ-45 Gigabit LAN Port
- Both USB 2.0 Ports
- All four USB 3.1 Gen1 Ports
- All three USB 2.0 headers
- Both USB 3.1 Gen1 headers
- Vertical Type A USB 3.1 Gen1 (located next to RAM slots and PCH)
- All six SATA3 6.0 Gb/s connectors by Intel
- All three PCI Express 3.0 x16 slots (tested with NV 1080 Ti dGPU)
- Both PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter)
- HD Audio Jack (Audio output tested only)
- Front Audio Jack (Audio output tested only)
not (yet) working:
- both SATA3 6.0 Gb/s connectors by ASMedia ASM1061 (fix will soon
be merged)
not (yet) tested:
- IR header
- COM Port header
- DisplayPort
- eSATA connector
- PS/2 Mouse/Keyboard Port
- HDMI-In Port
- PCI slots
Change-Id: I78791aa9877a3ad79bf8b896c583fedf37e96d9a
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84672
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This port was done via autoport and subsequent manual tweaking.
Working:
- Haswell MRC.bin
- All four DDR3/DDR3L DIMM slots
- S3 suspend and resume
- D-Sub Port
- DVI-D Port
- HDMI Port
- RJ-45 Gigabit LAN Port
- Both rear USB 2.0 Ports
- All four rear USB 3.1 Gen1 Ports
- Both USB 2.0 headers
- USB 3.1 Gen1 header
- All six SATA3 6.0 Gb/s connectors by Intel
- Both PCI Express 3.0 x16 slots (Tested with RX 550 PCIe x8 GPU)
- PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter)
- HD Audio Jack (Audio output tested only)
- Front Audio Jack (Audio output tested only)
not (yet) tested:
- PCI slots
- IR header
- COM Port header
- PS/2 Mouse/Keyboard Port
- Optical SPDIF Out Port
Change-Id: I3c13c068d899588eda80b9957127bcb6ccf8bab0
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85926
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This port was done via autoport and subsequent manual tweaking.
Working:
- Haswell MRC.bin
- All four DDR3/DDR3L DIMM slots
- HDMI-Out Port
- DVI-D Port
- D-Sub Port
- RJ-45 Gigabit LAN Port
- All four USB 2.0 Ports
- All four USB 3.1 Gen1 Ports
- Vertical Type A USB 3.1 Gen1 (located next to RAM slots)
- All six SATA3 6.0 Gb/s connectors
- PCI Express 3.0 x16 slot (tested with AMD RX 550 dGPU)
- PCI Express 2.0 x16 slot (tested with AMD RX 550 dGPU)
- Both PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter)
- HD Audio Jack (Audio output tested only)
- Front Audio Jack (Audio output tested only)
not working:
- Both USB 3.1 Gen1 headers (also not working on vendor firmware,
possible hardware defect)
not (yet) tested:
- IR header
- COM Port header
- USB 2.0 headers
- PS/2 Mouse/Keyboard Port
- HDMI-In Port
- PCI slots
Change-Id: I2f01f2f25e0a4bcec10b075b574757250a5e5256
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When writing key_protect_setting to PMIC, PMIC expects receiving 1 byte
per write. PMIC would receive unexpected zero byte if using
mt6685_write16. Fix the write operation by using mt6685_write8.
TEST=Build pass.
BUG=b:388666377
Signed-off-by: Lu Tang <lu.tang@mediatek.corp-partner.google.com>
Change-Id: Ib6e79642e813e7a1f0d38243e9c4db5a699cc9e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86035
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the issue where the DUT cannot power on during S5. When writing
key_protect_setting to PMIC, PMIC expects receiving 1 byte per write.
PMIC would receive unexpected zero byte if using mt6363_write16. Fix the
write operation by using mt6363_write8.
TEST=Build pass, DUT can power on during S5.
BUG=b:388666377
Change-Id: I0a7c0d2fa1f93a55731b4b58923d6f80a4c4be89
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86034
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
MMINFRA_GCE_DDREN_SEL is a setting for switching the DRAM transaction
ACK from SPM: 0, non-SPM: 0x1.
In MT8196, SPM has masked all the DDR requests, so this setting should
be set to non-SPM whenever mminfra is powering on. Otherwise, GCE will
hang when accessing DRAM.
BUG=b:379039600
TEST=boot up ok, GCE can access DRAM continuously
Change-Id: I30309b0426f803e28858eb15652a649927f94c7e
Signed-off-by: Jason-jh Lin <jason-jh.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
In the current eDP initialization flow, eDP is configured and enabled
before display data pipe (DDP) initialization. The init flow is wrong,
because eDP should be enabled only after DDP is correctly set up. The
wrong flow may lead to garbage display between enabling eDP and
configuring DDP.
To fix the problem, the dptx_video_enable(true) call needs to be moved
after mtk_ddp_mode_set(). Introduce a new API mtk_edp_enable() for eDP
enablement, to be separated from the existing mtk_edp_init(). The fixed
eDP init flow is: mtk_edp_init -> mtk_ddp_mode_set -> mtk_edp_enable.
Change-Id: Ief847320caca1af1c6deb242dc224e7698a6603c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86028
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Run mtk_fsp_romstage.elf (MediaTek firmware support package for
romstage) in romstage to support power switch.
BUG=b:373797027
TEST=build pass, boot ok.
Load and run mtk_fsp with following logs:
[DEBUG] FMAP: area FW_MAIN_A found @ 402000 (1527552 bytes)
[INFO ] CBFS: Found 'fallback/mtk_fsp_romstage' @0xfc280 size 0x6bd in
mcache @0x00122518
[INFO ] VB2:vb2_digest_init() 1725 bytes, hash algo 2, HW acceleration
enabled
[INFO ] _start: MediaTek FSP_ROMSTAGE interface version: 1.0
[INFO ] mtk_fsp_load_and_run: run fallback/mtk_fsp_romstage at phase
0x30 done
Change-Id: Id223152e0bda71e99e72b34c91fea8f8841e824b
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86015
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
