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mb/trulo/var/uldrenite: Update eMMC DLL settings

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Based on Intel eMMC tuning result, update eMMC DLL settings.

BUG=b:388438199
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I276ebbfc29e3899cbacdc2353648017a3fa5b8a6
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86016
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Dtrain Hsu 2025-01-16 16:51:28 +08:00 • committed by Subrata Banik
commit 2d69e28636
1 changed files with 5 additions and 5 deletions
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10
src/mainboard/google/brya/variants/uldrenite/overridetree.cb
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@ -26,7 +26,7 @@ chip soc/intel/alderlake
# Refer to EDS-Vol2-42.3.8.
# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x311b"
# EMMC TX DATA Delay 2
# Refer to EDS-Vol2-42.3.9.
@ -34,7 +34,7 @@ chip soc/intel/alderlake
# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C282928"
# EMMC RX CMD/DATA Delay 1
# Refer to EDS-Vol2-42.3.10.
@ -42,7 +42,7 @@ chip soc/intel/alderlake
# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C19593B"
# EMMC RX CMD/DATA Delay 2
# Refer to EDS-Vol2-42.3.12.
@ -53,13 +53,13 @@ chip soc/intel/alderlake
# 11: Reserved
# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004E"
register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10026"
# EMMC Rx Strobe Delay
# Refer to EDS-Vol2-42.3.11.
# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01313"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1