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mb/*: Remove old USB configs from SNB/bd82x6x boards, part 2

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As of commit a911b75848 ("mb/*: Remove old USB configurations from
SNB/bd82x6x boards") USB configurations are drawn exclusively from
devicetree. These stuff should have been removed then.

Change-Id: I03b1bce9a12aa687a7c65db79efc2cddc1708a79
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
This commit is contained in:
Keith Hui 2025-01-11 07:13:01 -05:00 • committed by Elyes Haouas
commit 1c24ae5550
7 changed files with 0 additions and 125 deletions
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18
src/mainboard/lenovo/t430s/variants/t430s/romstage.c
View file

@ -4,27 +4,9 @@
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <ec/lenovo/pmh7/pmh7.h>
#include <types.h>
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 0 }, /* P0:, OC 0 */
{ 1, 1, 1 }, /* P1: (EHCI debug), OC 1 */
{ 1, 1, 3 }, /* P2: OC 3 */
{ 1, 0, -1 }, /* P3: no OC */
{ 1, 2, -1 }, /* P4: no OC */
{ 1, 1, -1 }, /* P5: no OC */
{ 1, 1, -1 }, /* P6: no OC */
{ 0, 1, -1 }, /* P7: empty, no OC */
{ 1, 1, -1 }, /* P8: smart card reader, no OC */
{ 1, 0, 5 }, /* P9: (EHCI debug), OC 5 */
{ 1, 0, -1 }, /* P10: fingerprint reader, no OC */
{ 1, 1, -1 }, /* P11: bluetooth, no OC. */
{ 0, 0, -1 }, /* P12: wlan, no OC */
{ 1, 1, -1 }, /* P13: camera, no OC */
};
void mainboard_early_init(int s3resume)
{
u8 enable_peg = get_uint_option("enable_dual_graphics", 0);

18
src/mainboard/lenovo/t430s/variants/t431s/romstage.c
View file

@ -1,24 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <northbridge/intel/sandybridge/raminit.h>
#include <southbridge/intel/bd82x6x/pch.h>
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 0 }, /* SSP1: right */
{ 1, 0, 1 }, /* SSP2: left, EHCI Debug */
{ 1, 1, 3 }, /* SSP3: dock USB3 */
{ 1, 1, -1 }, /* B0P4: wwan USB */
{ 1, 1, 2 }, /* B0P5: dock USB2 */
{ 0, 0, -1 }, /* B0P6 */
{ 0, 0, -1 }, /* B0P7 */
{ 1, 2, -1 }, /* B0P8: unknown */
{ 1, 0, -1 }, /* B1P1: smart card reader */
{ 0, 2, 5 }, /* B1P2 */
{ 1, 1, -1 }, /* B1P3: fingerprint reader */
{ 0, 0, -1 }, /* B1P4 */
{ 1, 1, -1 }, /* B1P5: wlan USB */
{ 1, 1, -1 }, /* B1P6: Camera */
};
void mb_get_spd_map(struct spd_info *spdi)
{

17
src/mainboard/lenovo/t520/early_init.c
View file

@ -34,23 +34,6 @@ static void hybrid_graphics_init(void)
pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 1, 0 }, /* P0 left dual conn, OC 0 */
{ 1, 1, 1 }, /* P1 system onboard USB (eSATA), (EHCI debug), OC 1 */
{ 1, 2, -1 }, /* P2: wimax / WLAN */
{ 1, 1, -1 }, /* P3: WWAN, no OC */
{ 1, 1, -1 }, /* P4: smartcard, no OC */
{ 1, 1, -1 }, /* P5: ExpressCard, no OC */
{ 0, 2, -1 }, /* P6: empty */
{ 0, 2, -1 }, /* P7: to touch panel, no OC */
{ 1, 1, 4 }, /* P8: left dual conn, OC4 */
{ 1, 4, 5 }, /* P9: to system subcard back right, (EHCI debug), OC 5 */
{ 1, 1, -1 }, /* P10: fingerprint reader, no OC */
{ 1, 2, -1 }, /* P11: bluetooth, no OC. */
{ 1, 1, -1 }, /* P12: docking, no OC */
{ 1, 1, -1 }, /* P13: CAMERA (LCD), no OC */
};
void mainboard_early_init(int s3resume)
{
hybrid_graphics_init();

19
src/mainboard/lenovo/x1_carbon_gen1/early_init.c
View file

@ -2,27 +2,8 @@
#include <console/console.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
const struct southbridge_usb_port mainboard_usb_ports[] = {
/* enabled, current, OC pin */
{ 0, 3, 0 }, /* P00 disconnected */
{ 1, 1, 1 }, /* P01 left or right */
{ 0, 1, 3 }, /* P02 disconnected */
{ 1, 3, -1 },/* P03 WWAN */
{ 0, 1, 2 }, /* P04 disconnected */
{ 0, 1, -1 },/* P05 disconnected */
{ 0, 1, -1 },/* P06 disconnected */
{ 0, 2, -1 },/* P07 disconnected */
{ 0, 1, -1 },/* P08 disconnected */
{ 1, 2, 5 }, /* P09 left or right */
{ 1, 3, -1 },/* P10 FPR */
{ 1, 3, -1 },/* P11 Bluetooth */
{ 1, 1, -1 },/* P12 WLAN */
{ 1, 1, -1 },/* P13 Camera */
};
static unsigned int get_spd_index(void)
{
const int spd_gpio_vector[] = {25, 45, -1};

17
src/mainboard/msi/ms7707/early_init.c
View file

@ -11,20 +11,3 @@ void mainboard_pch_lpc_setup(void)
reg16 |= (1 << 13); // WOL Enable Override (WOL_EN_OVRD)
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xa4, reg16);
}
const struct southbridge_usb_port mainboard_usb_ports[] = {
{1, 0, 0},
{1, 0, 0},
{1, 0, 1},
{1, 0, 1},
{1, 0, 2},
{1, 0, 2},
{1, 0, 3},
{1, 0, 3},
{1, 0, 4},
{1, 0, 4},
{1, 0, 6},
{1, 0, 5},
{1, 0, 5},
{1, 0, 6},
};

18
src/mainboard/supermicro/x9sae/early_init.c
View file

@ -2,7 +2,6 @@
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6776/nct6776.h>
@ -10,23 +9,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI)
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 0 },
{ 1, 0, 0 },
{ 1, 0, 1 },
{ 1, 0, 1 },
{ 1, 0, 2 },
{ 1, 0, 2 },
{ 1, 0, 3 },
{ 1, 0, 3 },
{ 1, 0, 4 },
{ 1, 0, 4 },
{ 1, 0, 6 },
{ 1, 0, 5 },
{ 1, 0, 5 },
{ 1, 0, 6 },
};
void bootblock_mainboard_early_init(void)
{
nuvoton_pnp_enter_conf_state(GLOBAL_DEV);

18
src/mainboard/supermicro/x9scl/early_init.c
View file

@ -5,7 +5,6 @@
#include <device/pnp_ops.h>
#include <bootblock_common.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6776/nct6776.h>
#include <superio/nuvoton/wpcm450/wpcm450.h>
@ -18,23 +17,6 @@
#define SUPERIO_INITVAL(reg, data) {(reg), (data)}
#define SUPERIO_BANK(x) SUPERIO_INITVAL(0x07, (x))
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 0 }, /* ? USB0 1d.0 port 1 */
{ 1, 0, 0 }, /* ? USB1 1d.0 port 2 */
{ 1, 0, 1 }, /* ? USB2 1d.0 port 3 */
{ 1, 0, 1 }, /* ? USB3 1d.0 port 4 */
{ 1, 0, 2 }, /* ? USB4 1d.0 port 5 */
{ 1, 0, 2 }, /* ? USB5 1d.0 port 6 */
{ 1, 0, 3 }, /* ? ??? 1a.0 port 1 */
{ 1, 0, 3 }, /* ? BMC 1a.0 port 2 */
{ 1, 0, 4 }, /* ? ??? 1a.0 port 3 */
{ 1, 0, 4 }, /* ? USB11 1a.0 port 4 */
{ 1, 0, 6 }, /* ? USB12 1a.0 port 5 */
{ 1, 0, 5 }, /* ? USB13 1a.0 port 6 */
{ 1, 0, 5 },
{ 1, 0, 6 },
};
static const uint8_t superio_initvals[][2] = {
/* Global config registers */
SUPERIO_INITVAL(0x1a, 0xc8),