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mb/google/fatcat/var/felino: Modify the felino config for probing TPM I2C

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Modify the configuration to detect TPM I2C correctly.

BUG=b:388982526
TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino

Change-Id: I093c0bad181f133e601f3270de68c0848f847ccf
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
This commit is contained in:
Tongtong Pan 2025-01-14 10:31:29 +08:00 • committed by Subrata Banik
commit 1457e9b994
3 changed files with 14 additions and 7 deletions
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1
src/mainboard/google/fatcat/Kconfig
View file

@ -118,6 +118,7 @@ config DRIVER_TPM_I2C_BUS
hex
default 0x03 if BOARD_GOOGLE_MODEL_FATCAT
default 0x01 if BOARD_GOOGLE_FRANCKA
default 0x01 if BOARD_GOOGLE_FELINO
config HAVE_SLP_S0_GATE
def_bool n

14
src/mainboard/google/fatcat/variants/felino/gpio.c
View file

@ -278,7 +278,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_F14: NC */
PAD_NC(GPP_F14, NONE),
/* GPP_F15: GSC_PCH_INT_ODL */
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
PAD_CFG_GPI_APIC(GPP_F15, NONE, PLTRST, LEVEL, INVERT),
/* GPP_F16: NC */
PAD_NC(GPP_F16, NONE),
/* GPP_F17: NC */
@ -399,12 +399,12 @@ static const struct pad_config early_gpio_table[] = {
/* GPP_H09: UART0_BUF_TXD */
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
/* GPP_H06: I2C3_SDA_PSS */
PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
/* GPP_H07: I2C3_SCL_PSS */
PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
/* GPP_D15: SPI_TPM_INT_N */
PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST, LEVEL, INVERT),
/* GPP_H21: PCH_I2C_GSC_SDA */
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
/* GPP_H22: PCH_I2C_GSC_SCL */
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
/* GPP_F15: SPI_TPM_INT_N */
PAD_CFG_GPI_APIC(GPP_F15, NONE, PLTRST, LEVEL, INVERT),
};
/* Pad configuration in romstage */

6
src/mainboard/google/fatcat/variants/felino/overridetree.cb
View file

@ -47,6 +47,12 @@ chip soc/intel/pantherlake
[DDI_PORT_A] = DDI_ENABLE_HPD,
}"
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
}"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |