This updates the Kconfig for Google Fatcat mainboards to include
`SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON` option to ensure
compatibility with Panther Lake pre-production silicon. This selection
aligns these boards with the necessary pre-production silicon settings
BUG=b:424355826
TEST=Ensure mainboards like fatcat4es and fatcatnuvo4es have
`SOC_INTEL_PANTHERLAKE_PRE_PRODUCTION_SILICON` config enabled.
Change-Id: Icde96976e0e3ccfc543bc948d2923e0f84e7da68
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88219
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due to Pujjoquince does not have ISH, thus define bit 29 in
firmware_config to indicate ISH presence per platform.
BUG=b:417599885
BRANCH=none
TEST= Use the command ls /dev/cros_ and no cros_ish option
will appear
Change-Id: I286300eadf7991d3a30936f5904ff3eef4480039
Signed-off-by: erin liang <erin.liang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88364
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add HYNIX H54G46CYRBX267 as id 0, and add HYNIX H54G56CYRBX247
as id 1, resulting in the list below:
DRAM Part Name ID to assign
K4U6E3S4AB-MGCL 0 (0000)
K4UBE3D4AB-MGCL 1 (0001)
MT53E1G32D2NP-046 WT:B 1 (0001)
NT6AP512T32BL-J1 2 (0010)
NT6AP1024F32BL-J1 3 (0011)
CXDB4CBAM-ML-A 2 (0010)
H54G56CYRBX247 1 (0001)
H54G46CYRBX267 0 (0000)
BUG=430792154
TEST=Use part_id_gen to generate related settings
Change-Id: I6ea840862b4b7b728a351425da9fc4052c201e3c
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88419
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As far back as the x201, Lenovo's EC ACPI has treated 128 as an invalid
value, and returned a corrected value when it is reported/read from EC
RAM. Drop the ME workaround, which most H8-equipped boards select, in
favor of Lenovo's logic, since both accomplish the same result.
Change-Id: Icdc91e439ec30c8263de5810a13e75f7595472a5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88416
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Looking at the ACPI dumps of many older Thinkpads, most do not have a
second thermal zone (zone 1), they only use zone 0. This doesn't seem
to be a problem for most boards in the tree currently, but newer boards
(such as the T480) are reporting critical temperature errors on zone 1,
due to differences in the EC RAM layout (ie, TMP1 is not valid).
To mitigate this issue with the T480 (and likely other newer boards),
only include the ACPI code for thermal zone 1 for boards which need it.
Explicitly select it for those boards based on ACPI dump analysis and
model similarity.
Change-Id: Ic022f2e14b2cae74656c0ac85ba8410d50cdc9de
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Using Kconfig options instead of chip registers allows for newer boards
which do not implement BT/WWAN detection to not compile in the GPIO-
related parts, which are only valid for older (pre-FSP) platforms.
Change-Id: Ibfe738adfc75abfaf078c6b7ff5472a1424909f5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88414
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the caboc variant of the brox reference board by copying
the template files to a new directory named for the variant.
BUG=b:420796212
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_CABOC.
Change-Id: I424933574873defe5289fbe7309270583cb8a49e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88379
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable USB3 WWAN since the issue is fixed with the latest schematics.
Schematic version: 500E_S3A0_TWL_MB_FVT_20250527
BUG=b:424945817
BRANCH=none
TEST=Remove Verify USB3 WWAN with the latest schematics.check the WWAN USB3 interface is now working properly..
Change-Id: I30eb74a8456bc63c964269822e0b10135d24aa1f
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Schematic version: 500E_S3A0_TWL_MB_FVT_20250527
BUG=b:424945817
BRANCH=none
TEST=Verify USB3 WWAN with the latest schematics.
Change-Id: I30eb74a8456bc63c964269822e0b10135d24aa1f
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88340
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because of intel suggestion, the change will fix the sensor driver
could be "probe fail" issue. So update mipi camera parameters' value.
Change:
1. CSI Camera lanes from 2 to 4.
2. Value of index 0 of frequency link array from 720000000 to 360000000
3. Value of index 1 of frequency link array from 360000000 to 180000000
BUG=b:395763555
BRANCH=none
TEST=Build and boot to OS and check mipi camera function.
Change-Id: Ieea6d99182df9c5aa9ca7a7f72f031921c24199e
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Update fingerprint enable pin status to keep the module disabled
and in reset in firmware. This allows the module to be enabled
and released from reset during kernel boot via ACPI.
BUG=b:411558536
BRANCH=none
TEST= Boot to OS and into VT2, use ectool --name=cros_fp version
will return fingerprint version information and check the
functionality works.
Change-Id: I98707e0e6ba550f6b7d75a84e72843c3873fa56c
Signed-off-by: erin liang <erin.liang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88287
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This change adds the necessary configuration for the elan
touchscreen (ELAN9004) device, connected to I2C bus 16.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset, stop and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:430467732
TEST=emerge-nissa coreboot and elan touchscreen can work well.
Change-Id: I08a32eae272d5ef93f1c89bcb96b9ba50c037624
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
The PS/2 Keyboard and Mouse won't work in Microsoft Windows 10 or 11 on
these tested HP variants:
- compaq_pro_6300
- compaq_8200_elite_sff
- compaq_8300_elite_sff
Unless the following line to acpi/superio.asl was added:
#include <drivers/pc80/pc/ps2_controller.asl>
Without this patch PS/2 ports only work in EDK2, SeaBIOS, GRUB 2 and
Linux.
Dmesg output for comparison without and with patch (trimmed):
[ 0.232601] pnp: PnP ACPI: found 16 devices
...
[ 0.231146] pnp: PnP ACPI: found 18 devices
...
TEST=Boot Windows 10 / 11 verify that PS/2 Keyboard & Mouse works!
Although only 3 models were tested and this common option affects all
snb_ivb_desktops variants I'm pretty confident it will work on all the
others since it also works on boards from other Manufacturers from Dell
and GIGABYTE even single port with splitter cable.
Change-Id: I21c10cc24c25887ab822a5889de5eec3b3537ac9
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88322
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This HP desktop comes in 4 different CPU variants. This port was made
using the Pentium 3558U @ 1.70GHz variant with 2*4GB DDR3L SODIMM RAM
modules with a single SATA adapter cable. Other variants may come with
an M2.SSD slot which may need other devicetree.cb PCIe / SATA edits!
Model: HP 260 G1 DM Business PC
Regulatory Model: TPC-1011-DM
Product No.: N9F00EA#ABH, 260G1eD/G3558U/500h/4X/50f NL
Mainboard: E131920, 791401-002
Pure autoport (initial commit) doesn't boot, further patches bring up
general Haswell fixes, vendor/product naming corrected, RAM SPD MAP
slot detection, (m)PCIe fixes enabling onboard LAN and mini PCIe slot
and some NPCD379 code from other HP desktops make most superio related
functions work for this PC.
Flash instructions:
After setting the FDO jumper on the motherboard the whole ROM can be
dumped, however writing is locked for some part of the BIOS region.
An external flasher ch341a_spi (3.3v mod) was used with a SOIC 8 pomona
probe to flash the MX25L6406E in situ without any issues. Only the
power of the USB programmer was used, and the board's main PSU was
disconnected during flash!
Tested:
- coreboot 25.06-77-g812d0e2f626d as base
- EDK2 (MrChromebox/2502)
- SeaBIOS 1.16.3
- SystemAgent mrc.bin (haswell/peppy)
- libgfxinit textmode (SeaBIOS) / framebuffer (EDK2)
- DP / DP++ (HDMI) & VGA all available during POST, BOOT and OS
- Pentium 3558U
- RAM single 4GB and dual slot 8GB total with 1.35V DDR3L SODIMMS
4GB DDR3-1600 - SK Hynix HMT451S6BFR8A-PB (2016-W01)
HMT451S6BFR8A-PB NO AA 1601
1Rx8 PC3L-12800S-11-13-B4
4GB DDR3 1600 - Kingston 9905469-143.A00LF (2016-W05)
KTH-X3CL/4G
1.35V
BPMK0831621
9905469-143.A00LF
0000007258426-PW005291
- Fedora MATE 42 (Kernel 6.14)
- KDE NEON 6.4 (Kernel 6.11)
- Audio Outputs HDMI, Headphone, Lineout & Speaker (left&right chan.)
- USB2/3 all ports
- Realtek onboard Gb LAN
- miniPCIe slot + its embedded USB (Intel Wireless AC3160HMW+BT)
- SATA port using the original flatcable adapter
- PowerButton (Poweron/Poweroff/Wake)
- LEDs HDD & POWER (both off during suspend)
- Shutdown/Reboot/Suspend
- Strip down the Intel ME/TXE firmware (make menuconfig)
- Disabling ME HECI (manually disable in devicetree.cb)
- flashrom -p internal -c "MX25L6406E/MX25L6408E" (read & write)
Not tested:
- Broadwell mrc.bin
- Front Microphone Port
- USBDEBUG
- VBIOS
Not working:
- FAN control its either full OFF or full ON see instruction!
- Wake on LAN
- Ethernet is detected as PCIe slot connected instead of onboard
- Disable Intel ME PCI interface (make menuconfig)
- Windows 10/11 USB detection/hotplug issues (all USB ports)
- Haswell NRI (posts & boots but will shutdown in less than a minute)
FAN instructions:
If the superio HWM (devicetree.cb node pnp 2e.8) is set to on, the FAN
will turn OFF during post and stays OFF. If the superio HWM pnp 2e.8 is
set to off the FAN will stay ON and will rampup after post in roughly a
minute to its maximum RPM and will stay that way (current default)!
The data.vbt blob was extracted using debugfs from the OEM firmware
v2.19 which enables all video outputs Displayport / DP++ (HDMI) and VGA.
Theoretically like the "compaq_8200_elite_sff" it should be possible
to flash internally using a 2 step flash procedure using a minimized ME
a small SeaBIOS based coreboot and a temporary flash layout inside the
writeable BIOS region.
Change-Id: Ifedd9f700e5f3875d3577fa56225d9d49d622b47
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88326
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update TPM related default value for TPM_TIS_ACPI_INTERRUPT based on
schematic_1433518 after mapping GPP_B to GPE0_DW1.
BUG=b:394208231, b:430001789
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I890c6779a24eaa7804594003466e8660af4becc2
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88358
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch updates the GPE configuration for Ocelot in baseboard
devicetree based on schematic_1433518.
BUG=b:394208231, b:430001789
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I60bcf586ab8653732925bfd9393baef226519c3a
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88106
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously, the touchscreen IRQ pin was not correctly configured to
GPP_F18_IRQ, which caused an unexpected interrupt storm and led to
the touchscreen becoming unresponsive. This change sets it to the
correct configuration. (schematics version 20250611_v31)
BUG=b:430200649
TEST= Ensure the touchscreen is working properly.
Ensure the interrupt count increases only when the screen is touched
via 'cat /proc/interrupts | grep ELAN'
Change-Id: I20cc9632df76acdfafd2968ece0dde8ee95cc791
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
When battery is not present, reduce power limits to below 45W,avoid
inability to enter the system.
To avoid poor efficiency of the adapter, leave a margin and set the
powerlimit to 38W.
This will check the current battery status and configure cpu power
limits using current PD power value.
BUG=b:418695656
BRANCH=None
TEST=
1、built (emerge-nissa coreboot chromeos-bootimage) and push ap firmware
to dut.
2、Connect 15W machine without battery to 45W adapter and check if it
starts up properly.
3、Use ec command “cbmem -c | grep PL“ to check if the PL4 value is 38
watts.
Log result:[INFO] CPU PL4 = 38 Watts
Change-Id: Iadd43c75ea9235b7ba0e3b97ef460280c13ef1e3
Signed-off-by: Baozhen Yang <yangbaozhen5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Because of internal misunderstanding, modify mipi camera FW_CONFIG
Schematic version: 500E_S3A0_TWL_MB_FVT_20250527
BUG=b:395763555
BRANCH=none
TEST=Boot to OS and verify the mipi camera device are set based on
fw_config.
Change-Id: Id2d62d14bdfd6ad925c5a0c1a9799350a93e57e2
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88352
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Align USB3 Type-A and the related GPIO settings with Pujjolo schematic
(Pujjolo_Pujjoquince_MB_EVT_20250523.pdf).
BUG=b:427962702
TEST= Connect USB 3.0 devices to the Type-A interface and use "lsusb -t"
command to verify the connection
Change-Id: I559dc8105258b91ca89b2f10644e4f95d6a4a085
Signed-off-by: Ben Kao <ben.kao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88290
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit enhances the Kinmen variant of the Fatcat mainboard by
introducing an `fw_config` field for AUDIO. This field includes an
`AUDIO_UNKNOWN` option, providing a clear state when no specific audio
configuration is selected or known.
Furthermore, a probe statement for `AUDIO_ALC721_SNDW` has been added
to the `hda` device. This ensures that the system can correctly identify
and initialize the Realtek ALC721 audio codec when present.
These changes improve the flexibility and accuracy of audio
configuration and detection for the Kinmen board.
BUG=b:430205874
TEST=Able to boot google/kinmen to UI without valid Audio configuration.
Change-Id: I86634a4a49c4006584fc808719b2891186953a51
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88367
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces an `AUDIO_UNKNOWN` option to the `fw_config` for
the Francka variant of the Fatcat mainboard. This allows for a default
or fallback state when a specific audio configuration isn't known or
desired.
Additionally, this change introduces audio probe statements that allow
the system to boot successfully even if `FW_CONFIG` is set to
`AUDIO_UNKNOWN`, effectively disabling the audio controller in such
cases.
This prevents boot failures when an unsupported or unknown audio codec
is selected, improving system robustness.
BUG=b:430205874
TEST=Able to boot google/francka to UI without valid Audio
configuration.
Change-Id: I34f7fe5f0509cbddfd3648afb087786373fcf8df
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
This commit modifies the Fatcat mainboard configuration to ensure the
Audio controller is only enabled when a valid `FW_CONFIG` is selected.
This change introduces audio probe statements that allow the
system to boot successfully even if `FW_CONFIG` is set to
`AUDIO_UNKNOWN`, effectively disabling the audio controller in such
cases.
This prevents boot failures when an unsupported or unknown audio codec
is selected, improving system robustness.
BUG=b:430205874
TEST=Able to boot google/fatcat to UI without valid Audio configuration.
Change-Id: I7d1fa07978725129c2651f258894f3590e0a69eb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88365
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
This patch configures Interrupt, Enable and Reset pins for FPS.
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: Ida4fab8da007403898e6843d5161249a5093fd54
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88351
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides option to enable/disable ISH.Removed the
copies and redundant ISH pins from GPIO.c
Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86
BUG=b:394208231
TEST= Build Ocelot and verify it compiles without any error.
Change-Id: I02bfa6b90b1c37a1d69d094804b4153e191a29af
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88329
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes redundant SNDW GPIO mapping that was already present
in fw_config.c and applied as per FW_CONFIG.
BUG=b:427091370
TEST=Boot beep verification is possible using google/fatcat.
Change-Id: Ibeca991b9e855792df48073d2138b9c7ec130c41
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88350
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set the CRFP device to use GPIO for the power status. This causes an
ACPI `_STA()` function to be generated that returns the power status of
the CRFP device, rather than always returning `0x1`. This `_STA()`
function can be used during boot to skip enabling the device (and
performing the associated sleep) if the device is already powered on.
BUG=b:428793056
TEST=Boot the board and make sure the FPMCU was booted once
(e.g. examine FPMCU console logs)
TEST=Dump SSDT on kinmen
Scope (\_SB.PCI0.SPI0)
{
Device (CRFP)
{
...
...
PowerResource (PR00, 0x00, 0x0000)
{
Method (_STA, 0, Serialized) // _STA: Status
{
0x5D = \_SB.PCI0.GTXS /* External reference */
Local0
If (!Local0)
{
Return (Zero)
}
0x27 = \_SB.PCI0.GTXS /* External reference */
Local0
Local0 ^= One
If (Local0)
{
Return (Zero)
}
Return (One)
}
Method (_ON, 0, Serialized) // _ON_: Power On
{
Local0 = _STA ()
If ((Local0 == One))
{
Return (Zero)
}
\_SB.PCI0.CTXS (0x27)
\_SB.PCI0.STXS (0x5D)
Sleep (0x03)
\_SB.PCI0.STXS (0x27)
}
Method (_OFF, 0, Serialized) // _OFF: Power Off
{
\_SB.PCI0.CTXS (0x27)
\_SB.PCI0.CTXS (0x5D)
}
}
}
}
Change-Id: Ia3054c61dfab185d124b3aae8df9e80aa6afc71a
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88338
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the necessary configuration for the focaltech
touchscreen (FTSC1000) device, connected to I2C bus 38.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
Datasheet: FT8112_Data_Sheet_V0.2_HKC20240415.pdf
BUG=b:429335394
TEST=emerge-nissa coreboot and focaltech touchscreen can work well.
Change-Id: Ic1c4bea599db23d5bc760bb7a54a2581cb293ce3
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88284
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board does not use the board_id-feature hence the code can be
removed.
Change-Id: I18c67580d4611b4c53248315937277bed53bd1ea
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This mainboard does not have an embedded controller (EC), therefore
remove the code for it.
Change-Id: Ib37b3cc257f7ac4af6a6505a3e43c9e5275fcd3f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88262
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard will just have a single VBT in cbfs which will be named
as the default name is (vbt.bin). There is no need to chose between
different configurations for the VBT selection. Therefore, remove the
corresponding code.
Change-Id: Ia72e8bae23c15476c362e456dc8358bec3b102a5
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This mainboard is not going to use Type-C subsystem. Therefore, disable
and remove the config data for it.
Change-Id: I2d9e53bf63b41811040f84cfe9dedf275f1059e4
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88260
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Siemens boards store their memory configuration data (SPD) in a field
inside the HWInfo block (which itself is located in CBFS). This patch
removes all *spd.hex-files and uses HWInfo instead for the SPD data
source. In addition, the memory data swizzling is updated to reflect
the board wiring so that DRAM can work properly.
Change-Id: I63d6e7c4543b7d99a4b1815c8ee81efcb6a87b94
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
While reviewing CB:87192 that deals with this option on another
mainboard, it was found that northbridge/intel/sandybridge
actually could not handle this option (present on Ivy Bridge
only anyway) properly. It would only factor 544MB into memory
calculations while telling IGD it can use 1024MB.
Until a fix can be implemented there, remove this option from
Ivy Bridge mainboards.
Change-Id: I0c87c52ef050cca54e050de3d41603c4ab29740b
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88294
Reviewed-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Values here above 512M are:
1. Inconsistent with Intel IVB datasheet vol.2, document #326765;
2. Apparently not properly supported by nb/intel/sandybridge.
Take them out until a fix can be implemented.
Change-Id: I6183f447af2816d00c9f6d78329113cd9c584191
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88293
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board is missing option values for 256MB and up.
Make complete by referencing asus/p8x7x-series and Intel IVB
datasheet vol.2, document #326765.
Intel datasheet lists an additional 1GB option for Ivy Bridge
CPUs, but since nb/intel/sandybridge/northbridge.c has been
found to not handle this setting properly when doing memory
calculations, a fix is needed there before it can be included.
It was not an option for Sandy Bridge anyway.
BUG=https://ticket.coreboot.org/issues/581
Change-Id: Id89290a673b0e5dbc72c11c097aeb70d410adeab
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Recent development of the "pro_6300" variant fixed the 4th sata port,
using "register sata_port_map" = "0x17" in "overridetree.cb" the same
is valid for the following 2 variants:
- compaq_8300_elite_sff
- compaq_8200_elite_sff
BUG=581#note-22
TEST=grub2 output & dmesg output
p4
�����������������������������������������
� Boot Menu �
�����������������������������������������
Device Path :
Select a Boot Device PciRoot(0x0)/Pci(0x1F,
0x2)/Sata(0x4,0xFFFF,0
UEFI Shell x0)
USB Device
SATA: hp DVD A DH16ABSH
dmesg | grep SATA | grep link
[ 4.994271] ata1: SATA link down (SStatus 0 SControl 300)
[ 5.304068] ata2: SATA link down (SStatus 0 SControl 300)
[ 5.616102] ata3: SATA link down (SStatus 0 SControl 300)
[ 5.920122] ata5: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
Change-Id: Idcef5854e1e97380bec12374411ddfdb50395c29
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88304
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When battery is not present, reduce power limits to below 45W,
avoid inability to enter the system.
To avoid poor efficiency of the adapter, leave a margin and set the powerlimit to 38w.
This will check the current battery status and configure cpu power
limits using current PD power value.
BUG=b:418695656
BRANCH=None
TEST=
1、built(emerge-nissa coreboot chromeos-bootimage) and push ap firmware to dut.
2、Connect 15W machine without battery to 45W adapter and check if it starts up properly.
3、Use ec command “cbmem -c | grep PL“ to check if the PL4 value is 38 watts.
Change-Id: I72429052f5b3d25e56076176728498357a298cdd
Signed-off-by: Baozhen Yang <yangbaozhen5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88282
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The IOT version of FSP is inconsistent at resuming from S3,
so switch to the client version.
Change-Id: Ifadfebf53e20bc82e6272ea28e5bc443b9829545
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88055
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Enable Realtek ALC722 and ALC1320 soundwire codec for francka.
Refer to the main board schematic(1224A) and
audio board schematic(1106A).
BUG=b:420516709
TEST=Build and boot and check the ssdt dump PCI0.HDAS.SNDW.
Scope (\_SB.PCI0.HDAS.SNDW)
Device (SW00)
Name (_ADR, 0x000030025D072201) // _ADR: Address
Name (_DDN, "Headset Codec") // _DDN: DOS Device Name
Scope (\_SB.PCI0.HDAS.SNDW)
Device (SW20)
Name (_ADR, 0x000230025D132001) // _ADR: Address
Name (_DDN, "Speaker Amp") // _DDN: DOS Device Name
Scope (\_SB.PCI0.HDAS.SNDW)
Device (SW30)
Name (_ADR, 0x000330025D132001) // _ADR: Address
Name (_DDN, "Speaker Amp") // _DDN: DOS Device Name
Change-Id: I542d94fd792272d3b7d75538671ba2f59c331a1e
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88022
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Because of the internal misunderstanding, so now correct the right fw
config of wifi SAR id number from 18 to 21 to 17 to 20.
BUG=b:395763555
BRANCH=none
TEST=Build and boot to OS and check coreboot log to check the wifi SAR table could work fine.
Change-Id: Ib006996fb8887a36feb5dfe71baef58fa74c35f7
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88200
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The power LED may be disabled by GPP_D1. The pin is PWM capable, so
configure it in PWM mode with a frequency of 0.5Hz, duty cycle of 50%
when entering sleep.
The result is that the power LED toggles on/off every second.
TEST=Boot to Windows 10, enter S3, and wake. The power LED will blink
when system is asleep and glow continuously when awake.
Change-Id: I121e0ef3e47aec1cacdace3f2af47a3fdacf69cf
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Correct UART1 TX/RX pad configuration in early_gpio.c from NF2
to NF1. This enables proper UART1 signaling on GPP_D17 and GPP_D18
when operating in native mode.
This change is based on guidance from Intel Doc. No. 648094.
TEST=Patched and booted board. Confirmed UART1 communication
works via serial adapter. Loopback test passed.
Change-Id: Ib1f5ee17e6f3d8a845d024e6b8593606b0430b6f
Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88195
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
