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mb/google/ocelot: Update GPE configuration

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This patch updates the GPE configuration for Ocelot in baseboard
devicetree based on schematic_1433518.

BUG=b:394208231, b:430001789
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: I60bcf586ab8653732925bfd9393baef226519c3a
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88106
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
P, Usha 2025-06-16 11:58:30 +05:30 • committed by Nick Vaccaro
commit 0660fe50de
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb
View file

@ -1,7 +1,7 @@
chip soc/intel/pantherlake
# GPE configuration
register "pmc_gpe0_dw0" = "GPP_A"
register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw0" = "GPP_VGPIO"
register "pmc_gpe0_dw1" = "GPP_B"
register "pmc_gpe0_dw2" = "GPP_E"
# For Ocelot variants with microchip EC: