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mb/hp: Add HP 260 G1 DM Business PC (Haswell)

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This HP desktop comes in 4 different CPU variants. This port was made
using the Pentium 3558U @ 1.70GHz variant with 2*4GB DDR3L SODIMM RAM
modules with a single SATA adapter cable. Other variants may come with
an M2.SSD slot which may need other devicetree.cb PCIe / SATA edits!

Model: HP 260 G1 DM Business PC
Regulatory Model: TPC-1011-DM
Product No.: N9F00EA#ABH, 260G1eD/G3558U/500h/4X/50f NL
Mainboard: E131920, 791401-002

Pure autoport (initial commit) doesn't boot, further patches bring up
general Haswell fixes, vendor/product naming corrected, RAM SPD MAP
slot detection, (m)PCIe fixes enabling onboard LAN and mini PCIe slot
and some NPCD379 code from other HP desktops make most superio related
functions work for this PC.

Flash instructions:
After setting the FDO jumper on the motherboard the whole ROM can be
dumped, however writing is locked for some part of the BIOS region.
An external flasher ch341a_spi (3.3v mod) was used with a SOIC 8 pomona
probe to flash the MX25L6406E in situ without any issues. Only the
power of the USB programmer was used, and the board's main PSU was
disconnected during flash!

Tested:
 - coreboot 25.06-77-g812d0e2f626d as base
 - EDK2 (MrChromebox/2502)
 - SeaBIOS 1.16.3
 - SystemAgent mrc.bin (haswell/peppy)
 - libgfxinit textmode (SeaBIOS) / framebuffer (EDK2)
 - DP / DP++ (HDMI) & VGA all available during POST, BOOT and OS
 - Pentium 3558U
 - RAM single 4GB and dual slot 8GB total with 1.35V DDR3L SODIMMS
	4GB DDR3-1600 - SK Hynix HMT451S6BFR8A-PB (2016-W01)
	    HMT451S6BFR8A-PB NO AA 1601
	    1Rx8 PC3L-12800S-11-13-B4
	4GB DDR3 1600 - Kingston 9905469-143.A00LF (2016-W05)
	    KTH-X3CL/4G
	    1.35V
	    BPMK0831621
	    9905469-143.A00LF
	    0000007258426-PW005291
 - Fedora MATE 42 (Kernel 6.14)
 - KDE NEON 6.4 (Kernel 6.11)
 - Audio Outputs HDMI, Headphone, Lineout & Speaker (left&right chan.)
 - USB2/3 all ports
 - Realtek onboard Gb LAN
 - miniPCIe slot + its embedded USB (Intel Wireless AC3160HMW+BT)
 - SATA port using the original flatcable adapter
 - PowerButton (Poweron/Poweroff/Wake)
 - LEDs HDD & POWER (both off during suspend)
 - Shutdown/Reboot/Suspend
 - Strip down the Intel ME/TXE firmware (make menuconfig)
 - Disabling ME HECI (manually disable in devicetree.cb)
 - flashrom -p internal -c "MX25L6406E/MX25L6408E" (read & write)

Not tested:
 - Broadwell mrc.bin
 - Front Microphone Port
 - USBDEBUG
 - VBIOS

Not working:
 - FAN control its either full OFF or full ON see instruction!
 - Wake on LAN
 - Ethernet is detected as PCIe slot connected instead of onboard
 - Disable Intel ME PCI interface (make menuconfig)
 - Windows 10/11 USB detection/hotplug issues (all USB ports)
 - Haswell NRI (posts & boots but will shutdown in less than a minute)

FAN instructions:
If the superio HWM (devicetree.cb node pnp 2e.8) is set to on, the FAN
will turn OFF during post and stays OFF. If the superio HWM pnp 2e.8 is
set to off the FAN will stay ON and will rampup after post in roughly a
minute to its maximum RPM and will stay that way (current default)!

The data.vbt blob was extracted using debugfs from the OEM firmware
v2.19 which enables all video outputs Displayport / DP++ (HDMI) and VGA.

Theoretically like the "compaq_8200_elite_sff" it should be possible
to flash internally using a 2 step flash procedure using a minimized ME
a small SeaBIOS based coreboot and a temporary flash layout inside the
writeable BIOS region.

Change-Id: Ifedd9f700e5f3875d3577fa56225d9d49d622b47
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88326
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Walter Sonius 2025-07-06 09:55:15 +02:00 • committed by Matt DeVillier
commit d5bce8c420
14 changed files with 445 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

29
src/mainboard/hp/260_g1_dm/Kconfig Normal file
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## SPDX-License-Identifier: GPL-2.0-only
if BOARD_HP_260_G1_DM
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_8192
select CPU_INTEL_HASWELL
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_GMA_HAVE_VBT
select INTEL_LYNXPOINT_LP
select MAINBOARD_HAS_LIBGFXINIT
select MAINBOARD_HAS_TPM1
select MEMORY_MAPPED_TPM
select NORTHBRIDGE_INTEL_HASWELL
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_LYNXPOINT
select SUPERIO_NUVOTON_NPCD378
config MAINBOARD_DIR
default "hp/260_g1_dm"
config MAINBOARD_PART_NUMBER
default "260 G1 DM"
config USBDEBUG_HCD_INDEX
default 1
endif

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src/mainboard/hp/260_g1_dm/Kconfig.name Normal file
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## SPDX-License-Identifier: GPL-2.0-only
config BOARD_HP_260_G1_DM
bool "260 G1 DM"

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src/mainboard/hp/260_g1_dm/Makefile.mk Normal file
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## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

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src/mainboard/hp/260_g1_dm/acpi/ec.asl Normal file
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/* SPDX-License-Identifier: CC-PDDC */
/* Please update the license if adding licensable material. */

10
src/mainboard/hp/260_g1_dm/acpi/platform.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
Method(_WAK, 1)
{
Return(Package() {0, 0})
}
Method(_PTS, 1)
{
}

3
src/mainboard/hp/260_g1_dm/acpi/superio.asl Normal file
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/* SPDX-License-Identifier: CC-PDDC */
/* Please update the license if adding licensable material. */

8
src/mainboard/hp/260_g1_dm/board_info.txt Normal file
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Category: desktop
Board URL: https://support.hp.com/us-en/product/setup-user-guides/hp-260-g1-desktop-mini-pc/7375834
ROM IC: MX25L6406E
ROM protocol: SPI
Flashrom support: y
ROM package: SOIC8
ROM socketed: no
Release year: 2015

BIN
src/mainboard/hp/260_g1_dm/data.vbt Normal file
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Binary file not shown.

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src/mainboard/hp/260_g1_dm/devicetree.cb Normal file
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chip northbridge/intel/haswell
register "dq_pins_interleaved" = "1"
register "ec_present" = "false"
register "gpu_ddi_e_connected" = "1"
register "spd_addresses" = "{0x50, 0, 0x51, 0}"
chip cpu/intel/haswell
device cpu_cluster 0x0 on ops haswell_cpu_bus_ops end
end
device domain 0x0 on
ops haswell_pci_domain_ops
subsystemid 0x103c 0x8000 inherit
device pci 00.0 on end # ULT Host bridge
device pci 02.0 on end # Internal graphics VGA controller
device pci 03.0 on end # Mini-HD audio
chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
register "docking_supported" = "1"
register "gen1_dec" = "0x00fc0a01"
register "gen2_dec" = "0x00fc0b01"
register "gpe0_en_4" = "0x2046"
register "sata_port0_gen3_dtle" = "0x7"
register "sata_port1_gen3_dtle" = "0x9"
register "sata_port_map" = "0x1"
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # xHCI Controller
device pci 15.0 off end # Serial I/O DMA
device pci 15.1 off end # I2C0
device pci 15.2 off end # I2C1
device pci 15.3 off end # GSPI0
device pci 15.4 off end # GSPI1
device pci 15.5 off end # UART0
device pci 15.6 off end # UART1
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 17.0 off end # SDIO
device pci 19.0 off end # Intel Gigabit Ethernet
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 off end # PCIe Port #1
device pci 1c.1 off end # PCIe Port #2
device pci 1c.2 on end # Onboard Realtek LAN
device pci 1c.3 on end # X1PCIEXP11
device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6
device pci 1d.0 on end # USB2 EHCI #1
device pci 1f.0 on # LPC bridge
chip superio/common
device pnp 2e.ff on # passes SIO base addr to SSDT gen
chip superio/nuvoton/npcd378
device pnp 2e.0 off end # Floppy
device pnp 2e.1 off # Parallel port
# global
# serialice: Vendor writes:
irq 0x14 = 0xd0
irq 0x1c = 0xa8
irq 0x1d = 0x01
irq 0x22 = 0x3f
irq 0x1a = 0xa0
# dumped from superiotool:
irq 0x1b = 0x1e
irq 0x27 = 0x08
irq 0x2a = 0x00
irq 0x2d = 0x21
# parallel port
io 0x60 = 0x278
irq 0x70 = 0x07
drq 0x74 = 0x04
end
device pnp 2e.2 off # COM1
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 off # COM2, IR
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.4 on # LED control
io 0x60 = 0x0a20
# IOBASE[0h] = bit0 LED red / green
# IOBASE[0h] = bit1-4 LED PWM duty cycle
# IOBASE[1h] = bit6 SWCC
io 0x62 = 0x0aa0
# IOBASE [0h] = GPES
# IOBASE [1h] = GPEE
# IOBASE [4h:7h] = 32bit upcounter at 1Mhz
# IOBASE [8h:bh] = GPS
# IOBASE [ch:fh] = GPE
end
device pnp 2e.5 off # Mouse
irq 0x70 = 0xc
end
device pnp 2e.6 off # Keyboard
io 0x60 = 0x0060
io 0x62 = 0x0064
irq 0x70 = 0x01
# serialice: Vendor writes:
drq 0xf0 = 0x40
end
device pnp 2e.7 on # WDT ?
io 0x60 = 0x0a00
end
device pnp 2e.8 off # HWM
io 0x60 = 0x0b00
# IOBASE[0h:feh] HWM page
# IOBASE[ffh] bit0-bit3 page selector
drq 0xf0 = 0x20
drq 0xf1 = 0x01
drq 0xf2 = 0x40
drq 0xf3 = 0x01
drq 0xf4 = 0x66
drq 0xf5 = 0x66
drq 0xf6 = 0x66
drq 0xf7 = 0x01
end
device pnp 2e.f on # GPIO OD ?
drq 0xf1 = 0x97
drq 0xf2 = 0x01
drq 0xf5 = 0x0b
drq 0xfe = 0x80
end
device pnp 2e.15 off # BUS ?
io 0x60 = 0x0000
io 0x62 = 0x0000
end
device pnp 2e.1c on # Suspend Control ?
io 0x60 = 0x0a60
# writing to IOBASE[5h]
# 0x0: Power off
# 0x9: Power off and bricked until CMOS battery removed
end
device pnp 2e.1e off # GPIO ?
io 0x60 = 0x0000
drq 0xf4 = 0x00
# skip the following, as it
# looks like remapped registers
#drq 0xf5 = 0x06
#drq 0xf6 = 0x60
#drq 0xfe = 0x03
end
end
end
end
chip drivers/pc80/tpm
device pnp 4e.0 on end # TPM module
end
end
device pci 1f.2 on end # SATA Controller (AHCI)
device pci 1f.3 on end # SMBus
device pci 1f.6 off end # Thermal
end
end
end

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src/mainboard/hp/260_g1_dm/dsdt.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20141018
)
{
#include <acpi/dsdt_top.asl>
#include "acpi/platform.asl"
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/common/acpi/platform.asl>
/* global NVS and variables. */
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
#include <southbridge/intel/common/acpi/sleepstates.asl>
Device (\_SB.PCI0)
{
#include <northbridge/intel/haswell/acpi/hostbridge.asl>
#include <southbridge/intel/lynxpoint/acpi/pch.asl>
}
}

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src/mainboard/hp/260_g1_dm/gma-mainboard.ads Normal file
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-- SPDX-License-Identifier: GPL-2.0-or-later
with HW.GFX.GMA;
with HW.GFX.GMA.Display_Probing;
use HW.GFX.GMA;
use HW.GFX.GMA.Display_Probing;
private package GMA.Mainboard is
ports : constant Port_List :=
(DP1,
HDMI1,
DP2,
others => Disabled);
end GMA.Mainboard;

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src/mainboard/hp/260_g1_dm/gpio.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/lynxpoint/lp_gpio.h>
const struct pch_lp_gpio_map mainboard_lp_gpio_map[] = {
[0] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[2] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[3] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[4] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[5] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[6] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[7] = LP_GPIO_INPUT,
[8] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
.pirq = GPIO_PIRQ_APIC_ROUTE
},
[9] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
.pirq = GPIO_PIRQ_APIC_ROUTE
},
[10] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
.pirq = GPIO_PIRQ_APIC_ROUTE
},
[11] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[12] = LP_GPIO_OUT_LOW,
[13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
.pirq = GPIO_PIRQ_APIC_ROUTE
},
[14] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
.pirq = GPIO_PIRQ_APIC_ROUTE
},
[15] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[18] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[19] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[20] = LP_GPIO_NATIVE,
[21] = LP_GPIO_NATIVE,
[22] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[23] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[24] = LP_GPIO_OUT_LOW,
[25] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[28] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[29] = LP_GPIO_NATIVE,
[30] = LP_GPIO_NATIVE,
[31] = LP_GPIO_NATIVE,
[32] = LP_GPIO_NATIVE,
[33] = LP_GPIO_NATIVE,
[34] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, .owner = GPIO_OWNER_GPIO },
[35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, .owner = GPIO_OWNER_GPIO },
[36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[37] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[38] = LP_GPIO_NATIVE,
[39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[40] = LP_GPIO_NATIVE,
[41] = LP_GPIO_NATIVE,
[42] = LP_GPIO_NATIVE,
[43] = LP_GPIO_NATIVE,
[44] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[45] = LP_GPIO_OUT_LOW,
[46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
.pirq = GPIO_PIRQ_APIC_ROUTE
},
[47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
.pirq = GPIO_PIRQ_APIC_ROUTE
},
[48] = LP_GPIO_PIRQ,
[49] = LP_GPIO_PIRQ,
[50] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
.pirq = GPIO_PIRQ_APIC_ROUTE
},
[51] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
.pirq = GPIO_PIRQ_APIC_ROUTE
},
[52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
.pirq = GPIO_PIRQ_APIC_ROUTE
},
[53] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
.pirq = GPIO_PIRQ_APIC_ROUTE
},
[54] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
.pirq = GPIO_PIRQ_APIC_ROUTE
},
[55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO,
.pirq = GPIO_PIRQ_APIC_ROUTE
},
[56] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[57] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[58] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[60] = LP_GPIO_NATIVE,
[61] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[62] = LP_GPIO_NATIVE,
[63] = LP_GPIO_NATIVE,
[64] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[65] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[66] = LP_GPIO_NATIVE,
[67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[69] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[70] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[71] = LP_GPIO_NATIVE,
[72] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[73] = LP_GPIO_NATIVE,
[74] = LP_GPIO_NATIVE,
[75] = LP_GPIO_NATIVE,
[76] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[77] = LP_GPIO_INPUT,
[78] = LP_GPIO_INPUT,
[79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[80] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[81] = LP_GPIO_NATIVE,
[82] = LP_GPIO_NATIVE,
[83] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[84] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[85] = LP_GPIO_INPUT,
[86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, .owner = GPIO_OWNER_GPIO },
[87] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[88] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[89] = LP_GPIO_INPUT,
[90] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
[92] = LP_GPIO_INPUT,
[93] = LP_GPIO_INPUT,
[94] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO },
LP_GPIO_END
};

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src/mainboard/hp/260_g1_dm/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
0x10ec0221, /* Codec Vendor / Device ID: Realtek */
0x103c8000, /* Subsystem ID */
11, /* Number of 4 dword sets */
AZALIA_SUBVENDOR(0, 0x103c8000),
AZALIA_PIN_CFG(0, 0x12, 0x400c0000),
AZALIA_PIN_CFG(0, 0x14, 0x01014020),
AZALIA_PIN_CFG(0, 0x17, 0x90170110),
AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x1a, 0x02a11030),
AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x1d, 0x40500001),
AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x21, 0x0221102f),
};
const u32 pc_beep_verbs[0] = {};
AZALIA_ARRAY_SIZES;

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/lynxpoint/pch.h>
void mainboard_config_rcba(void)
{
}
const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
/* FIXME: Length and Location are computed from IOBP values, may be inaccurate */
/* Length, Enable, OCn#, Location */
{ 0x0080, 1, 1, USB_PORT_MINI_PCIE },
{ 0x0080, 1, 0, USB_PORT_MINI_PCIE },
{ 0x0040, 1, 3, USB_PORT_BACK_PANEL },
{ 0x0080, 1, 3, USB_PORT_DOCK },
{ 0x0080, 1, 2, USB_PORT_MINI_PCIE },
{ 0x0080, 1, 2, USB_PORT_MINI_PCIE },
{ 0x0040, 1, 1, USB_PORT_BACK_PANEL },
{ 0x0040, 1, 1, USB_PORT_BACK_PANEL },
};
const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
{ 1, 1 },
{ 1, 0 },
{ 1, 3 },
{ 1, 3 },
};