Use GPP_C08 as the GPIO_PCH_WP.
BUG=b:409472563
Test=TEST=wp status update verified by toggling it on and off.
Change-Id: I0f6c7c051b2d38a787fe3bb21266a6ef6ebc487b
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87413
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Two ME current working state definitions are missing. They are
needed for CB:85413. Get them from intelmetool.
Change-Id: Ie163c4b29155e3fd44f0cb3096f825c84da37559
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87394
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The memory dump was done for the 1.80 (2023-04-07) version of the
vendor's UEFI.
Change-Id: I649e2c3ae715651b5f0eadc9b52e61e4deae77a1
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
It's an ACPI spec violation for a device to have both an _ADR and
a _HID method, so prefer the latter if a HID value is specified
via the chip registers.
Change-Id: I5d84dbea52595e61df56a5ff779d5e0ee0d84bdf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87248
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On SoCs like Glinda, CPU cores may exhibit slight variations in
maximum boost frequency, and the L3 cache can be composed of
multiple blocks with different sizes and unique IDs.
Add helper functions,
1. get_max_boost_frequency() to compute max boost frequenncy.
2. ap_stash_core_info() to update core_info struct with max boost
frequency & all L3 cache block uniq ID & its size.
To accurately determine the total L3 cache size:
1. Retrieve L3 cache information for each CPU core.
2. Identify the unique cache ID associated with each core.
3. Aggregate cache sizes for all unique cache IDs to compute the
total L3 cache size, ensuring correct summation when L3 cache
blocks have different sizes.
TEST=Build for Glinda SoC, with L3 cache = 16MB + 8MB. Ran command
'dmidecode -t 7' & verified L3 cache is 24MB(Previously it was
wrongly reported as 32MB).
Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85640
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the interrupts coming from the sensors into the ISH.
BUG=b:410645679
Change-Id: I2acaed1900e248cfe7fcc81201c6991a9741f26c
Signed-off-by: Yuval Peress <peress@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87333
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the kinmen variant of the fatcat reference board by copying
the fatcat files to a new directory named for the variant.
BUG=b:409148565
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_KINMEN
2. Run part_id_gen tool without any errors
Change-Id: I51e388e61f102216f6ce9233c87c1915596602be
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87317
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Control ISH device and corresponding GPIOs using a FW_CONFIG field.
BUG=b:410645679
TEST=Enable/Disable ISH using the new FW_CONFIG field.
Change-Id: I69805116722535d77c7fd7701df261e0faa9138f
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Yuval Peress <peress@google.com>
Add a DSD with the HotPlugSupportInD3, as when it RTD3, the device
will appear as not-present. This will cause Windows to constantly
try to enable it, causing an endless loop of the device becoming
visible.
Test=build and boot `starlabs/starlite_adl`, check CNVi is always
visible in device manager.
Change-Id: I598ab173074522e9d5af002782c5d3ec7691a815
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87325
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a DSD with the HotPlugSupportInD3, as when it RTD3, the device
will appear as not-present. This will cause Windows to constantly
try to enable it, causing an endless loop of the device becoming
visible.
Test=build and boot `starlabs/starlite_adl`, check Bluetooth is
always visible in device manager.
Change-Id: I51a2c764ebe8b98b137eb0c98cfdcf2de6f4b86c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87324
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The previous implementation used _PS0 and _PS3 methods to control the
device power states. These are now replaced by a _S0W object to better
align with both coreboot's existing RTD3 driver, and the examples in
the ACPI specification.
This ensures that the Bluetooth device is recognized as capable of
reaching D3Hot when the system is in S0.
Test=build and boot starlite_adl with Windows and Linux, check Bluetooth
is functional and power draw decreases ~0.4W with no devices connected.
Change-Id: I6762b4a2a2454d4e4de2b25e3e5db17df5a8fc63
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The previous implementation used _PS0 and _PS3 methods to control the
device power states. These are now replaced by a _S0W object to better
align with both coreboot's existing RTD3 driver, and the examples in
the ACPI specification.
This ensures that the Bluetooth device is recognized as capable of
reaching D3Hot when the system is in S0.
Test=build and boot starlite_adl with Windows and Linux, check Bluetooth
is functional and power draw decreases ~0.4W with no devices connected.
Change-Id: I8aa49ee2220ba2ea39b343ea9a9486fca9f5f3d5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87241
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a check in the _ON method, similar to coreboot's ONSK handling
in its RTD3 driver, to determine whether the enable GPIO is already
asserted.
This prevents the OS from repeatedly invoking _ON, which can happen
because CNVi takes around 300ms to initialize after the GPIO is
enabled.
Change-Id: I53986aa11714666c12056460aa47396266a00a1c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add a check in the _ON method, similar to coreboot's ONSK handling
in its RTD3 driver, to determine whether the enable GPIO is already
asserted.
This prevents the OS from repeatedly invoking _ON, which can happen
because USB Bluetooth takes around 200ms to initialize after the
GPIO is enabled.
Change-Id: I424bc5f4c5b990fd5cb54daa3d6207828386c6f2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87239
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Guarding the existence of this register isn't necessary since we
guard its usage as well, and it complicates some subsequent changes,
so drop it.
Change-Id: I557c400e6dffeb9dc5b4b67a6cc6f15ba0ef27d0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87343
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The definitions were reversed, as PCH_S should use 0x44, and all others
0x80.
These values can be seen in SlimBootloader, and most UEFI firmwares.
Change-Id: Ia2e3866ef7d0756220f15a8d2bdf639ac6667738
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87323
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Similarly to how things are done for the I2C controller configuration,
implement the 'soc_get_i3c_ctrlr_info' function in all SoCs that have
I3C controllers. This function returns the contents of the SoC's
'i3c_ctrlr' array containing the base addresses and ACPI names of the
I3C controllers. This function will eventually be called by the common
I3C code which will be implemented in future patches.
Change-Id: Ib23fd896925770f49e567324bc8d12ac4c0944bd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87280
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These GPIOs are not used, so configure them accordingly.
Change-Id: I4e58a0e7545167db2c4034499bb99d3bfffc2277
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87164
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.
Set these all to sample on RSMRST.
Change-Id: I3f7133666743b8aa0dc39df54ffe3483a1ddd605
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87162
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that we require the FMAP to start at offset 0 in the flash, we can
assume this across the entire codebase and therefore simplify it on
several ends.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ieb1a23f9c0ae8c0e1c91287d7eb6f7f0abbf0c2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86771
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
For simplicity we are going to impose this restriction to coreboot.
Note however that this is only a restriction for coreboot itself. The
FMAP tool itself is still a generic tool that does not require the FMAP
to start at offset 0.
Add an defacto empty fmap_config.h to our test cases, since fmap.h now
includes fmap_config.h.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iba04ebdcd5557664a865d2854028dd811f052249
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Duty Cycle Correlation (DCC) analyzes and optimizes the relationship
between the duty cycles of multiple signals. This commit implements DCC
driver support to improve clock signals, power management, and
communication systems, enhancing system stability and performance.
These improvements will become more significant as the SoC ages.
BUG=b:389784352
BRANCH=rauru
TEST=Build pass, check dcc log:
[DEBUG] [DCC] DSU=0x0, LCPU=0x0, MCPU=0x17, BCPU=0x1b
Change-Id: I77e5cd951f45dad7a6e2e77c135b821e4179e019
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87320
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Make mt6359p_read_field() a general API usable by multiple drivers,
instead of a static function limited to the original driver.
BUG=b:379008996
BRANCH=none
TEST=build pass
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I2d9c3de9ad08f918a84fa63c1e9b3af7adc5974a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87336
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
We have to reset the USB hub as early as possible. Otherwise the USB3
hub may not be usable in the payload. This design has been introduced
since Cherry.
BUG=b:390357201
BRANCH=none
TEST=detect USB devices in depthcharge, and the log is like "Added USB
disk 2."
Change-Id: I4ee24aef2a887c8a30738912a8bf90f830a72bed
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87348
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Configure GPIO (XHCI_INIT_DONE) as output, so that payloads (for example
depthcharge) can assert it to notify EC to enable USB VBUS.
BUG=b:390357201
BRANCH=none
TEST=detect USB devices in depthcharge, and the log is like "Added USB
disk 2."
Change-Id: I99760ace3e87626f55c52dc4f8a30bab27cba345
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Since infracfg.h is not used in pmif_spi.c, remove its inclusion to
prevent build errors in projects that don't have infracfg.h.
BUG=b:379008996
BRANCH=none
TEST=build pass
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I09229ff370a53407b3f0c290704887de367ed80b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87339
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The flickering issue on ATNA40HQ01-0 panel can be resolved by setting
the swing level to the maximum (500mV). Therefore, add FORCE_MAX_SWING
quirk for ATNA40HQ01-0 panel where the fw config's OLED_WQXGA_PLUS field
is set to PRESENT. As OLED_WQXGA_PLUS is currently only available on
Navi, add an overridetree.cb for Navi.
BRANCH=rauru
BUG=b:392040003
TEST=check edp training pass and show log:
[INFO ] fw_config match found: OLED_WQXGA_PLUS=PRESENT
...
[INFO ] update_swing_preemphasis: Force swing setting to 3 (500 mV)
Change-Id: I4797ef8fe2257a9b578a969794d624d6e0f97d07
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87028
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Enable Acoustic noise mitigation for google/kanix and set slew rate
to 1/8 for IA and GT domains.
BUG=b:409934780
BRANCH=firmware-rex-15709.B
TEST=Able to build and boot to google/kanix
Change-Id: I73460715ac71428843cf505a21de15a6e4d15bea
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87349
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch overrides the FSP-M UART MMIO base address to ensure the FSP
GFX PEIM can output debug console messages when required.
Currently, the default UART MMIO base used by FSP-M/S might not be the
intended console UART for debug output in boot stages, particularly for
the GFX PEIM. By overriding it with the value derived from
`CONFIG_UART_FOR_CONSOLE` when either `PcdSerialDebugLevel` or
`SerialDebugMrcLevel` is non-zero, we ensure that debug logs are
directed to the configured console.
This change is crucial for debugging issues within the GFX PEIM
initialization process.
BUG=b:380375181
TEST=Verified that enabling FSP debug tokens after this change allows
viewing debug output from the GFX PEIM during display initialization.
Steps to reproduce:
1. Flash an AP FW image (`image.fatcat.serial.bin`).
2. Observe the absence of debug output from the GFX PEIM during display
initialization.
3. Dynamically enable the FSP debug token using
```
sudo cbfstool image-fatcat.serial.bin add-int -i 3 -n option/fsp_pcd_debug_level
```
4. Flash the modified AP FW image.
5. Observe debug output from the GFX PEIM during display initialization
```
[INFO]:[IsGraphicsDeviceSupported()]...
[INFO]:[GetVbtStartAddress()]
```
Change-Id: I835ef75cb3046217127823c92f708bfe4f3ff741
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87318
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add the Amston Lake (9W) with MCH_ID 0x4674 to the vr_config table.
Based on Intel docs 721616 rev 2.3.
BUG=NA
TEST=Boots on Intel Alder Lake CRB with X7433RE processor
Change-Id: I7249d3223ccbb1671a0b84da1c2347737e1aec89
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87246
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
When re-purposing the TCSS port to USB Type-A, PortResetMessageEnable
must be enabled for USB2 ports that are paired with the CPU XHCI port.
Set to USB2_PORT_TYPE_C to enable PortResetMessageEnable.
Also remove the workaround. (workaround CL:87053)
BUG=b:400809281
TEST=Connecting a USB3 speed device,using lsusb -t to check enumerated status.
with change:
/: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=xhci_hcd/2p, 20000M/x2
|__ Port 2: Dev 2, If 0, Class=Mass Storage, Driver=usb-storage, 5000M
without change:
/: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=xhci_hcd/12p, 480M
|__ Port 2: Dev 4, If 0, Class=Mass Storage, Driver=usb-storage, 480M
Change-Id: I7c4743d1d3bcf2567fdca9c0e07ed02c240d4baf
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87301
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Stop using magic values and use defines for Global Descriptor Table
(GDT) offsets. Use the existing defines from the corresponding headers.
Change-Id: I40c15f6341bdef9cd457619ec81e7ac624ec2d63
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87254
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A 'quirks' variable is added for panels that require special handling
in the display driver due to sensitivity to the eDP signal quality. The
display driver can then handle the special requests accordingly.
On Navi, the swing level needs to be increased to 3 (500mV) for the
ATNA40HQ01-0 panel to resolve a flickering issue.
BRANCH=rauru
BUG=b:392040003
TEST=check edp training pass and show log:
[INFO ] fw_config match found: OLED_WQXGA_PLUS=PRESENT
...
[INFO ] update_swing_preemphasis: Force swing setting to 3 (500 mV)
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: Ifa8c45050f61d3dff1fa7aed8fa8e435391a6f3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Select RESET_VECTOR_IN_RAM from the common SOC_AMD_COMMON_BLOCK_NONCAR
Kconfig option instead of selecting it in each AMD SoC's Kconfig which
selects SOC_AMD_COMMON_BLOCK_NONCAR.
From family 17h on, the AMD SoCs don't use cache as RAM (CAR) any more.
In most cases, including the coreboot case, the PSP puts coreboot's
bootblock into DRAM, thus RESET_VECTOR_IN_RAM needs to be selected.
There might be a case where the RESET_VECTOR_IN_RAM part isn't true, but
that isn't specific to a SoC generation, so even this unlikely case
doesn't prevent us from moving the selection of the Kconfig option to
the common non-CAR Kconfig option.
Change-Id: I87d7908f94505647f504f9d214e3c52f9c3a3715
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87322
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Re-enable the ISH for uldrenite and set the correct firmware name. ISH
was disabled on uldrenite due to a suspend issue that's no longer
there. Uldrenite PoR is to use the ISH. The issue was caused by a bug
in Intel's Zephyr HAL which included power management logic that
incorrectly handled one of the interrupts.
BUG=b:410645679
TEST=ISH device under lscpi.
# lspci -s 00:12.0 -knn
00:12.0 Serial controller [0700]: Intel Corporation Device [8086:54fc]
Subsystem: Intel Corporation Device [8086:7270]
Kernel driver in use: intel_ish_ipc
Kernel modules: intel_ish_ipc
Change-Id: I567fd43857da0023d063c0bb1b70c206dbee47f4
Signed-off-by: Yuval Peress <peress@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87313
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Move declaration of all CFR objects to a header file, so they don't
need to be guarded. Simplify the enablement of CFR options by creating
board-level Kconfig options as needed.
TEST=build/boot starbook MTL, TGL, ADL-N.
Change-Id: I43dfa6795708e9975b938ce1359629f6b9c4f1cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Use defines to create dxio descriptors as other mainboards.
Change-Id: I09e8a9fc37a7b775b76a3d8e5faaee7828f99000
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87220
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
