mb/asrock/imb-1222: Update GPIO config using new intelp2m
- use intelp2m, 2.5-a48e94c74b version; - add missing VGPIO groups. Change-Id: I351a32962561947296b115af96674a4cd1cb192d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Maxim Polyakov
Matt DeVillier
parent
a1210875e9
commit
eb68ff66eb
1 changed files with 98 additions and 1 deletions
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@ -4,7 +4,7 @@
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#include <mainboard/gpio.h>
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/*
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* Pad configuration was generated automatically using intelp2m utility
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* Pad configuration was generated automatically using intelp2m 2.5-a48e94c74b
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* [*] - allow FSP to configure this pad
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*/
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static const struct pad_config gpio_table[] = {
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@ -60,6 +60,7 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_B21, NONE),
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PAD_CFG_GPO(GPP_B22, 0, PLTRST),
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PAD_CFG_GPO(GPP_B23, 0, PLTRST),
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PAD_CFG_NF(GSPI0_CLK_LOOPBK, NONE, DEEP, NF1), /* GSPI0_CLK_LOOPBK */
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/* ------- GPIO Community 1 ------- */
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/* ------- GPIO Group GPP_C ------- */
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@ -124,6 +125,60 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_G6, NONE),
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PAD_NC(GPP_G7, NONE),
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/* ------- GPIO Group AZA ------- */
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PAD_CFG_NF(HDA_BCLK, NATIVE, DEEP, NF1), /* HDA_BCLK */
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PAD_CFG_NF(HDA_RST_B, NATIVE, DEEP, NF1), /* HDA_RST# */
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PAD_CFG_NF(HDA_SYNC, NATIVE, DEEP, NF1), /* HDA_SYNC */
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PAD_CFG_NF(HDA_SDO, NATIVE, DEEP, NF1), /* HDA_SDO */
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PAD_CFG_NF(HDA_SDI0, NATIVE, DEEP, NF1), /* HDA_SDI0 */
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PAD_CFG_NF(HDA_SDI1, NATIVE, DEEP, NF1), /* HDA_SDI1 */
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PAD_CFG_NF(I2S1_SFRM, NATIVE, DEEP, NF1), /* I2S1_SFRM */
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PAD_CFG_NF(I2S1_TXD, NATIVE, DEEP, NF1), /* I2S1_TXD */
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/* ------- GPIO Group VGPIO_0 ------- */
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PAD_CFG_GPO(CNV_BTEN, 0, DEEP),
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PAD_CFG_GPIO_BIDIRECT(CNV_GNEN, 0, NONE, DEEP, LEVEL, ACPI),
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PAD_CFG_GPIO_BIDIRECT(CNV_WFEN, 0, NONE, DEEP, LEVEL, ACPI),
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PAD_CFG_GPIO_BIDIRECT(CNV_WCEN, 1, NONE, DEEP, LEVEL, ACPI),
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PAD_CFG_GPI_TRIG_OWN(vCNV_GNSS_HOST_WAKE_B, NONE, DEEP, OFF, ACPI),
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PAD_CFG_GPIO_BIDIRECT(vSD3_CD_B, 0, NONE, DEEP, OFF, ACPI),
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PAD_CFG_GPIO_BIDIRECT(CNV_BT_HOST_WAKE_B, 0, NONE, DEEP, OFF, ACPI),
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PAD_CFG_GPIO_BIDIRECT(CNV_BT_IF_SELECT, 1, NONE, DEEP, LEVEL, ACPI),
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PAD_CFG_NF(vCNV_BT_UART_TXD, NONE, DEEP, NF1),
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PAD_CFG_NF(vCNV_BT_UART_RXD, NONE, DEEP, NF1),
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PAD_CFG_NF(vCNV_BT_UART_CTS_B, NONE, DEEP, NF1),
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PAD_CFG_NF(vCNV_BT_UART_RTS_B, NONE, DEEP, NF1),
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PAD_CFG_NF(vCNV_MFUART1_TXD, NONE, DEEP, NF1),
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PAD_CFG_NF(vCNV_MFUART1_RXD, NONE, DEEP, NF1),
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PAD_CFG_NF(vCNV_MFUART1_CTS_B, NONE, DEEP, NF1),
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PAD_CFG_NF(vCNV_MFUART1_RTS_B, NONE, DEEP, NF1),
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PAD_CFG_NF(vCNV_GNSS_UART_TXD, NONE, DEEP, NF1),
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PAD_CFG_NF(vCNV_GNSS_UART_RXD, NONE, DEEP, NF1),
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PAD_CFG_NF(vCNV_GNSS_UART_CTS_B, NONE, DEEP, NF1),
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PAD_CFG_NF(vCNV_GNSS_UART_RTS_B, NONE, DEEP, NF1),
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PAD_CFG_NF(vUART0_TXD, NONE, DEEP, NF1),
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PAD_CFG_NF(vUART0_RXD, NONE, DEEP, NF1),
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PAD_CFG_NF(vUART0_CTS_B, NONE, DEEP, NF1),
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PAD_CFG_NF(vUART0_RTS_B, NONE, DEEP, NF1),
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PAD_CFG_NF(vISH_UART0_TXD, NONE, DEEP, NF1),
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PAD_CFG_NF(vISH_UART0_RXD, NONE, DEEP, NF1),
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PAD_CFG_NF(vISH_UART0_CTS_B, NONE, DEEP, NF1),
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PAD_CFG_NF(vISH_UART0_RTS_B, NONE, DEEP, NF1),
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PAD_CFG_NF(vISH_UART1_TXD, NONE, DEEP, NF1),
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PAD_CFG_NF(vISH_UART1_RXD, NONE, DEEP, NF1),
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PAD_CFG_NF(vISH_UART1_CTS_B, NONE, DEEP, NF1),
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PAD_CFG_NF(vISH_UART1_RTS_B, NONE, DEEP, NF1),
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/* ------- GPIO Group VGPIO_1 ------- */
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PAD_CFG_NF(vCNV_BT_I2S_BCLK, NONE, DEEP, NF1),
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PAD_CFG_NF(vCNV_BT_I2S_WS_SYNC, NONE, DEEP, NF1),
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PAD_CFG_NF(vCNV_BT_I2S_SDO, NONE, DEEP, NF1),
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PAD_CFG_NF(vCNV_BT_I2S_SDI, NONE, DEEP, NF1),
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PAD_CFG_NF(vSSP2_SCLK, NONE, DEEP, NF1),
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PAD_CFG_NF(vSSP2_SFRM, NONE, DEEP, NF1),
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PAD_CFG_NF(vSSP2_TXD, NONE, DEEP, NF1),
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PAD_CFG_NF(vSSP2_RXD, NONE, DEEP, NF1),
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/* ------- GPIO Community 2 ------- */
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/* ------- GPIO Group GPD ------- */
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PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), /* BATLOW# */
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@ -138,6 +193,10 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), /* SLP_WLAN# */
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PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* SLP_S5# */
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PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), /* LANPHYPC */
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PAD_CFG_NF(SLP_LAN_B, NONE, RSMRST, NF1), /* SLP_LAN# */
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PAD_CFG_NF(SLP_SUS_B, NONE, RSMRST, NF1), /* SLP_SUS# */
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PAD_CFG_NF(WAKE_B, NONE, RSMRST, NF1), /* WAKE# */
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PAD_CFG_NF(DRAM_RESET_B, NONE, RSMRST, NF1), /* DRAM_RESET# */
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/* ------- GPIO Community 3 ------- */
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/* ------- GPIO Group GPP_K ------- */
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@ -233,7 +292,42 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_F22, NONE),
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PAD_CFG_GPO(GPP_F23, 0, PLTRST),
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/* ------- GPIO Group SPI ------- */
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PAD_CFG_NF(SPI0_IO_2, NATIVE, DEEP, NF1), /* SPI0_IO_2 */
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PAD_CFG_NF(SPI0_IO_3, NATIVE, DEEP, NF1), /* SPI0_IO_3 */
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PAD_CFG_NF(SPI0_MISO, NATIVE, DEEP, NF1), /* SPI0_MISO */
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PAD_CFG_NF(SPI0_MOSI, NATIVE, DEEP, NF1), /* SPI0_MOSI */
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PAD_CFG_NF(SPI0_CS2_B, NATIVE, DEEP, NF1), /* SPI0_CS2# */
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PAD_CFG_NF(SPI0_CS0_B, NATIVE, DEEP, NF1), /* SPI0_CS0# */
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PAD_CFG_NF(SPI0_CS1_B, NATIVE, DEEP, NF1), /* SPI0_CS1# */
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PAD_CFG_NF(SPI0_CLK, NATIVE, DEEP, NF1), /* SPI0_CLK */
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PAD_CFG_NF(SPI0_CLK_LOOPBK, NONE, DEEP, NF1), /* SPI0_CLK_LOOPBK */
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/* ------- GPIO Community 4 ------- */
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/* ------- GPIO Group CPU ------- */
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PAD_CFG_NF(HDACPU_SDI, NATIVE, DEEP, NF1), /* HDACPU_SDI */
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PAD_CFG_NF(HDACPU_SDO, NATIVE, DEEP, NF1), /* HDACPU_SDO */
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PAD_CFG_NF(HDACPU_SCLK, NATIVE, DEEP, NF1), /* HDACPU_SCLK */
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PAD_CFG_NF(PM_SYNC, NONE, DEEP, NF1), /* PM_SYNC */
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PAD_CFG_NF(PECI_IO, NONE, DEEP, NF1), /* PECI_IO */
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PAD_CFG_NF(CPUPWRGD, NONE, DEEP, NF1), /* CPUPWRG# */
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PAD_CFG_NF(THRMTRIP_B, NONE, DEEP, NF1), /* THRMTRIP# */
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PAD_CFG_NF(PLTRST_CPU_B, NONE, DEEP, NF1), /* PLTRST_CPU# */
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PAD_CFG_NF(PM_DOWN, NONE, DEEP, NF1), /* PM_DOWN */
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PAD_CFG_NF(TRIGGER_IN, DN_20K, DEEP, NF1), /* TRIGGER_IN */
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PAD_CFG_NF(TRIGGER_OUT, DN_20K, DEEP, NF1), /* TRIGGER_OUT */
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/* ------- GPIO Group JTAG ------- */
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PAD_CFG_NF(PCH_TDO, NATIVE, DEEP, NF1), /* PCH_TDO */
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PAD_CFG_NF(PCH_JTAGX, NATIVE, DEEP, NF1), /* PCH_JTAGX */
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PAD_CFG_NF(PROC_PRDY_B, NATIVE, DEEP, NF1), /* PROC_RDY# */
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PAD_CFG_NF(PROC_PREQ_B, NATIVE, DEEP, NF1), /* PROC_REQ# */
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PAD_CFG_NF(CPU_TRST_B, NATIVE, DEEP, NF1), /* CPU_TRST# */
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PAD_CFG_NF(PCH_TDI, NATIVE, DEEP, NF1), /* PCH_TDI */
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PAD_CFG_NF(PCH_TMS, NATIVE, DEEP, NF1), /* PCH_TMS */
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PAD_CFG_NF(PCH_TCK, NATIVE, DEEP, NF1), /* PCH_TCK */
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PAD_CFG_NF(ITP_PMODE, NATIVE, DEEP, NF1), /* ITP_PMODE */
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/* ------- GPIO Group GPP_I ------- */
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PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), /* DDPB_HPD0 */
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PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), /* DDPB_HPD1 */
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@ -250,6 +344,9 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPO(GPP_I12, 0, PLTRST),
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PAD_NC(GPP_I13, NONE),
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PAD_CFG_GPO(GPP_I14, 1, PLTRST),
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PAD_CFG_NF(SYS_PWROK, NONE, DEEP, NF1), /* SYS_PWROK */
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PAD_CFG_NF(SYS_RESET_B, NONE, DEEP, NF1), /* SYS_RESET# */
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PAD_CFG_NF(CL_RST_B, NONE, DEEP, NF1), /* CL_RST# */
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/* ------- GPIO Group GPP_J ------- */
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PAD_CFG_NF(GPP_J0, NONE, PLTRST, NF1), /* CNV_PA_BLANKING */
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