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mb/google/fatcat/var/felino: Use GPP_C08 for GPIO_PCH_WP

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Use GPP_C08 as the GPIO_PCH_WP.

BUG=b:409472563
Test=TEST=wp status update verified by toggling it on and off.

Change-Id: I0f6c7c051b2d38a787fe3bb21266a6ef6ebc487b
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87413
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Tongtong Pan 2025-04-21 10:12:37 +08:00 • committed by Subrata Banik
commit d14ebe3957
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
View file

@ -27,7 +27,7 @@
#define GPIO_SLP_S0_GATE GPP_F23
#elif CONFIG(BOARD_GOOGLE_FELINO)
#define EC_SYNC_IRQ GPP_E03_IRQ
#define GPIO_PCH_WP 0 /* TODO */
#define GPIO_PCH_WP GPP_C08
/* Used to gate SoC's SLP_S0# signal */
#define GPIO_SLP_S0_GATE GPP_D03
#elif CONFIG(BOARD_GOOGLE_KINMEN)

2
src/mainboard/google/fatcat/variants/felino/gpio.c
View file

@ -117,7 +117,7 @@ static const struct pad_config gpio_table[] = {
/* GPP_C07: NC */
PAD_NC(GPP_C07, NONE),
/* GPP_C08: PCH_WP_OD */
PAD_CFG_GPO(GPP_C08, 1, PLTRST),
PAD_CFG_GPI(GPP_C08, NONE, DEEP),
/* GPP_C09: PCIE_CLKREQ_SSD1_N */
PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
/* GPP_C10: NC */