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mb/google/brya/var/uldrenite: Use FW_CONFIG for ISH

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Control ISH device and corresponding GPIOs using a FW_CONFIG field.

BUG=b:410645679
TEST=Enable/Disable ISH using the new FW_CONFIG field.

Change-Id: I69805116722535d77c7fd7701df261e0faa9138f
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Yuval Peress <peress@google.com>
This commit is contained in:
Kapil Porwal 2025-04-16 23:54:29 +05:30 • committed by Matt DeVillier
commit d71a969758
2 changed files with 17 additions and 0 deletions
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5
src/mainboard/google/brya/variants/uldrenite/overridetree.cb
View file

@ -15,6 +15,10 @@ fw_config
option MB_C_TWO 0
option MB_C_ONE 1
end
field ISH 8 8
option ISH_DISABLE 0
option ISH_ENABLE 1
end
end
chip soc/intel/alderlake
@ -487,6 +491,7 @@ chip soc/intel/alderlake
probe DB_CELLULAR CELLULAR_RW350R
end # PCIE2 WWAN card
device ref ish on
probe ISH ISH_ENABLE
chip drivers/intel/ish
register "firmware_name" = ""uldrenite_ish.bin""
device generic 0 on end

12
src/mainboard/google/brya/variants/uldrenite/variant.c
View file

@ -40,6 +40,13 @@ static const struct pad_config lte_disable_pads[] = {
PAD_NC(GPP_H23, NONE),
};
static const struct pad_config ish_disable_pads[] = {
/* B5 : GPP_B5 ==> NC */
PAD_NC(GPP_B5, NONE),
/* B6 : GPP_B6 ==> NC */
PAD_NC(GPP_B6, NONE),
};
void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
{
if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_NONE))) {
@ -52,6 +59,11 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
gpio_padbased_override(padbased_table, lte_disable_pads,
ARRAY_SIZE(lte_disable_pads));
}
if (!fw_config_probe(FW_CONFIG(ISH, ISH_ENABLE))) {
printk(BIOS_INFO, "Disable ISH GPIO pins.\n");
gpio_padbased_override(padbased_table, ish_disable_pads,
ARRAY_SIZE(ish_disable_pads));
}
}
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)