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mb/starlabs/starfighter: Reconfigure PCH Strap GPIOs

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Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.

Set these all to sample on RSMRST.

Change-Id: I3f7133666743b8aa0dc39df54ffe3483a1ddd605
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87162
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2025-04-04 11:37:58 +01:00 • committed by Matt DeVillier
commit 08d15e1ea1
1 changed files with 11 additions and 24 deletions
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35
src/mainboard/starlabs/starfighter/variants/rpl/gpio.c
View file

@ -103,12 +103,21 @@ const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* Data */
PAD_CFG_GPO(GPP_E8, 1, DEEP), /* DRAM Sleep */
/* Config Straps [ Low / High ] */
PAD_CFG_GPO(GPP_B14, 0, RSMRST), /* Top Swap [ Disabled / Enabled ] */
PAD_CFG_GPO(GPP_B18, 0, RSMRST), /* Reboot Support [ Enabled / Disabled ] */
PAD_CFG_GPO(GPP_C2, 1, RSMRST), /* TLS Confidentiality [ Disabled / Enabled ] */
PAD_CFG_GPO(GPP_C5, 0, RSMRST), /* eSPI [ Enabled / Disabled ] */
PAD_CFG_GPO(GPP_E6, 0, RSMRST), /* JTAG ODT [ Disabled / Enabled ] */
PAD_CFG_GPO(GPP_H1, 0, RSMRST), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */
PAD_CFG_GPO(GPP_F2, 1, RSMRST), /* M.2 CNVi [ Enabled / Disabled ] */
PAD_CFG_GPO(GPP_F7, 0, RSMRST), /* MCRO LDO [ Disabled / Bypass ] */
PAD_CFG_GPO(GPD7, 0, RSMRST), /* RTC Clock Delay [ Disabled / 95ms ] */
/* GPD2: LAN Wake */
PAD_NC(GPD2, NONE),
/* GPD6: Sleep A */
PAD_NC(GPD6, NONE),
/* GPD7: Power Adapter Disable */
PAD_CFG_GPO(GPD7, 0, PWROK),
/* GPD9: Wireless LAN Sleep */
PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
/* GPD10: Sleep S5 */
@ -165,16 +174,12 @@ const struct pad_config gpio_table[] = {
PAD_NC(GPP_B10, NONE),
/* B12: PM SLP S0 */
PAD_NC(GPP_B12, NONE),
/* B14: Not Connected */
PAD_NC(GPP_B14, NONE),
/* B15: Not Connected */
PAD_NC(GPP_B15, NONE),
/* B16: Not Connected */
PAD_NC(GPP_B16, NONE),
/* B17: Not Connected */
PAD_NC(GPP_B17, NONE),
/* B18: Not Connected */
PAD_NC(GPP_B18, NONE),
/* B19: Not Connected */
PAD_NC(GPP_B19, NONE),
/* B20: Not Connected */
@ -190,18 +195,10 @@ const struct pad_config gpio_table[] = {
/* B25: Not Connected */
PAD_NC(GPP_B25, NONE),
/* C2: TLS Confidentiality Weak Internal PD 20K
Low: Disabled
High: Enabled */
PAD_CFG_GPO(GPP_C2, 1, PLTRST),
/* C3: SML 0 Clock */
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
/* C4: SML 0 Data */
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
/* C5: Boot Strap Weak Internal PD 20K
Low: ESPI
High: Disabled */
PAD_CFG_GPO(GPP_C5, 0, DEEP),
/* C8: Not Connected */
PAD_NC(GPP_C8, NONE),
/* C9: Not Connected */
@ -272,10 +269,6 @@ const struct pad_config gpio_table[] = {
PAD_NC(GPP_E2, NONE),
/* E5: Not Connected */
PAD_NC(GPP_E5, NONE),
/* E6: JTAG ODT No internal PD
Low: Disabled
High: Enabled */
PAD_CFG_GPO(GPP_E6, 0, DEEP),
/* E7: Embedded Controller SMI */
PAD_NC(GPP_E7, NONE),
/* E9: USB OverCurrent 0 */
@ -313,10 +306,6 @@ const struct pad_config gpio_table[] = {
PAD_NC(GPP_F5, NONE),
/* F6: Not used */
PAD_NC(GPP_F6, NONE),
/* F7: TBT LSX VCCIO Weak Internal PD 20K
Low: 1.8V
High: 3.3V */
PAD_CFG_GPO(GPP_F7, 0, DEEP),
/* F8: Not Connected */
PAD_NC(GPP_F8, NONE),
/* F9: EC Sleep S0 */
@ -340,8 +329,6 @@ const struct pad_config gpio_table[] = {
/* F23: Not Connected */
PAD_NC(GPP_F23, NONE),
/* H1: BFX Strap 2 Bit 3 Weak Internal PD 20K */
PAD_CFG_GPO(GPP_H1, 0, DEEP),
/* H3: Not Connected */
PAD_NC(GPP_H3, NONE),
/* H6: Not Connected */