mb/asrock/imb-1222: Remove comments for non-functional pads
Change-Id: I00a9ab77a9b4ea9b42a50fceffdde382241b6950 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Maxim Polyakov
Matt DeVillier
parent
b81b7a2014
commit
b6871ab330
1 changed files with 41 additions and 41 deletions
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@ -37,7 +37,7 @@ static const struct pad_config gpio_table[] = {
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/* ------- GPIO Group GPP_B ------- */
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PAD_NC(GPP_B0, NONE),
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PAD_CFG_GPO(GPP_B1, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_B1, 1, PLTRST),
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PAD_NC(GPP_B2, NONE),
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PAD_NC(GPP_B3, NONE),
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PAD_NC(GPP_B4, NONE),
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@ -65,10 +65,10 @@ static const struct pad_config gpio_table[] = {
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/* ------- GPIO Group GPP_C ------- */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */
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PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_C2, 1, PLTRST),
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0CLK */
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0DATA */
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PAD_CFG_GPO(GPP_C5, 0, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_C5, 0, PLTRST),
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PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1CLK */
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PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1DATA */
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PAD_NC(GPP_C8, NONE),
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@ -115,12 +115,12 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_D23, NONE),
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/* ------- GPIO Group GPP_G ------- */
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PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, ACPI), /* GPIO */
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PAD_CFG_GPO(GPP_G1, 1, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_G2, 1, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_G3, 1, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_G4, 1, DEEP), /* GPIO */
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PAD_CFG_GPO(GPP_G5, 1, DEEP), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_G0, NONE, DEEP, OFF, ACPI),
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PAD_CFG_GPO(GPP_G1, 1, DEEP),
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PAD_CFG_GPO(GPP_G2, 1, DEEP),
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PAD_CFG_GPO(GPP_G3, 1, DEEP),
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PAD_CFG_GPO(GPP_G4, 1, DEEP),
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PAD_CFG_GPO(GPP_G5, 1, DEEP),
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PAD_NC(GPP_G6, NONE),
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PAD_NC(GPP_G7, NONE),
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@ -133,7 +133,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* SLP_S3# */
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PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* SLP_S4# */
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PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), /* SLP_A# */
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PAD_CFG_GPO(GPD7, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPD7, 1, PLTRST),
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PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), /* SUSCLK */
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PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), /* SLP_WLAN# */
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PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* SLP_S5# */
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@ -141,30 +141,30 @@ static const struct pad_config gpio_table[] = {
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/* ------- GPIO Community 3 ------- */
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/* ------- GPIO Group GPP_K ------- */
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PAD_CFG_GPO(GPP_K0, 0, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_K1, 0, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_K2, 0, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_K3, 0, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_K4, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_K5, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_K0, 0, PLTRST),
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PAD_CFG_GPO(GPP_K1, 0, PLTRST),
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PAD_CFG_GPO(GPP_K2, 0, PLTRST),
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PAD_CFG_GPO(GPP_K3, 0, PLTRST),
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PAD_CFG_GPO(GPP_K4, 1, PLTRST),
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PAD_CFG_GPO(GPP_K5, 1, PLTRST),
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PAD_NC(GPP_K6, NONE),
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PAD_NC(GPP_K7, NONE),
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PAD_CFG_GPO(GPP_K8, 0, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_K9, 0, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_K10, 0, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_K11, 0, PLTRST), /* GPIO */
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PAD_CFG_GPI_SCI(GPP_K12, NONE, PLTRST, EDGE_SINGLE, INVERT), /* GPIO */
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PAD_NC(GPP_K13, NONE), /* GPIO */
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PAD_CFG_GPO(GPP_K14, 0, DEEP), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_K15, NONE, PLTRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPO(GPP_K16, 0, PLTRST), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_K17, NONE, PLTRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPO(GPP_K8, 0, PLTRST),
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PAD_CFG_GPO(GPP_K9, 0, PLTRST),
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PAD_CFG_GPO(GPP_K10, 0, PLTRST),
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PAD_CFG_GPO(GPP_K11, 0, PLTRST),
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PAD_CFG_GPI_SCI(GPP_K12, NONE, PLTRST, EDGE_SINGLE, INVERT),
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PAD_NC(GPP_K13, NONE),
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PAD_CFG_GPO(GPP_K14, 0, DEEP),
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PAD_CFG_GPI_TRIG_OWN(GPP_K15, NONE, PLTRST, OFF, ACPI),
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PAD_CFG_GPO(GPP_K16, 0, PLTRST),
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PAD_CFG_GPI_TRIG_OWN(GPP_K17, NONE, PLTRST, OFF, ACPI),
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PAD_NC(GPP_K18, NONE),
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PAD_NC(GPP_K19, NONE),
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PAD_CFG_GPI_TRIG_OWN(GPP_K20, NONE, PLTRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_K21, NONE, DEEP, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_K22, NONE, PLTRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_K23, NONE, PLTRST, OFF, ACPI), /* GPIO */
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PAD_CFG_GPI_TRIG_OWN(GPP_K20, NONE, PLTRST, OFF, ACPI),
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PAD_CFG_GPI_TRIG_OWN(GPP_K21, NONE, DEEP, OFF, ACPI),
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PAD_CFG_GPI_TRIG_OWN(GPP_K22, NONE, PLTRST, OFF, ACPI),
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PAD_CFG_GPI_TRIG_OWN(GPP_K23, NONE, PLTRST, OFF, ACPI),
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/* ------- GPIO Group GPP_H ------- */
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/* [*] GPP_H0 GPIO/SRCCLKREQ6# */
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@ -179,7 +179,7 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_H9, NONE),
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PAD_NC(GPP_H10, NONE),
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PAD_NC(GPP_H11, NONE),
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PAD_CFG_GPO(GPP_H12, 0, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_H12, 0, PLTRST),
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PAD_NC(GPP_H13, NONE),
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PAD_NC(GPP_H14, NONE),
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PAD_NC(GPP_H15, NONE),
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@ -196,10 +196,10 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_E0, NONE, PLTRST, NF1), /* SATAXPCIE0 */
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PAD_CFG_NF(GPP_E1, NONE, PLTRST, NF1), /* SATAXPCIE1 */
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PAD_CFG_NF(GPP_E2, NONE, PLTRST, NF1), /* SATAXPCIE2 */
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PAD_CFG_GPO(GPP_E3, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_E3, 1, PLTRST),
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PAD_NC(GPP_E4, NONE),
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PAD_CFG_GPI_SMI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT), /* GPIO */
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PAD_CFG_GPI_SMI(GPP_E6, NONE, PLTRST, EDGE_SINGLE, INVERT), /* GPIO */
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PAD_CFG_GPI_SMI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT),
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PAD_CFG_GPI_SMI(GPP_E6, NONE, PLTRST, EDGE_SINGLE, INVERT),
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PAD_NC(GPP_E7, NONE),
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PAD_CFG_NF(GPP_E8, UP_5K, PLTRST, NF1), /* SATALED# */
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PAD_NC(GPP_E9, NONE),
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@ -208,11 +208,11 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_E12, NONE),
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/* ------- GPIO Group GPP_F ------- */
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PAD_CFG_GPO(GPP_F0, 0, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_F0, 0, PLTRST),
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PAD_CFG_NF(GPP_F1, UP_5K, PLTRST, NF1), /* SATAXPCIE4 */
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PAD_CFG_GPO(GPP_F2, 0, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_F3, 0, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_F4, 0, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_F2, 0, PLTRST),
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PAD_CFG_GPO(GPP_F3, 0, PLTRST),
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PAD_CFG_GPO(GPP_F4, 0, PLTRST),
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PAD_NC(GPP_F5, NONE),
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PAD_NC(GPP_F6, NONE),
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PAD_NC(GPP_F7, NONE),
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@ -231,7 +231,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_F20, NONE, PLTRST, NF1), /* eDP_BKLTEN */
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PAD_CFG_NF(GPP_F21, NONE, PLTRST, NF1), /* eDP_BKLTCTL */
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PAD_NC(GPP_F22, NONE),
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PAD_CFG_GPO(GPP_F23, 0, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_F23, 0, PLTRST),
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/* ------- GPIO Community 4 ------- */
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/* ------- GPIO Group GPP_I ------- */
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@ -247,9 +247,9 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* DDPD_CTRLCLK */
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PAD_CFG_NF(GPP_I10, NONE, PLTRST, NF1), /* DDPD_CTRLDATA */
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PAD_NC(GPP_I11, NONE),
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PAD_CFG_GPO(GPP_I12, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_I12, 1, PLTRST),
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PAD_NC(GPP_I13, NONE),
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PAD_CFG_GPO(GPP_I14, 1, PLTRST), /* GPIO */
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PAD_CFG_GPO(GPP_I14, 1, PLTRST),
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/* ------- GPIO Group GPP_J ------- */
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PAD_CFG_NF(GPP_J0, NONE, PLTRST, NF1), /* CNV_PA_BLANKING */
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