To sync with the dramc_param_common.h change [1] from MediaTek's DRAM
blob, change the u32 config_dvfs field to u16 and add a new field
data_version. As all MediaTek SoCs using the structure are little endian
and currently only bit 0 is used for the config_dvfs field, this change
is backward compatible. Therefore, each SoC's DRAMC_PARAM_HEADER_VERSION
doesn't need to be bumped.
[1] commit a39b473a0a7d ("common/cros: Support storing data version in
full-k cached data")
FIXED=415715491
TEST=emerge-skywalker coreboot
BRANCH=none
Change-Id: Ifcda7d360aefe083fc08c974e6dc62d1c9c12b5e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87912
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces initial support for PCI Express on the
Qualcomm x1p42100 SoC.
Key changes include:
- Selecting `CONFIG_PCI` in Kconfig to enable general PCI subsystem
support for this SoC.
- Selecting `CONFIG_NO_ECAM_MMCONF_SUPPORT`, indicating that this
platform will not use the standard MMCONFIG ECAM for PCI
configuration space access. An alternative mechanism will be required.
- Adding `../common/pcie_common.c` to the ramstage build if `CONFIG_PCI`
is enabled, incorporating common PCIe helper functions.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: I53e8bb3ce8551e8fa8c4b1cd39d89e12226c32f1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87858
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces `bootblock_soc_early_init` API for early SoC
initialization sequence in the bootblock.
- `bootblock_soc_early_init()`: This function now handles very early
initialization steps (before console init), specifically
`soc_mmu_init()` when the bootblock is not compressed.
- `bootblock_soc_init()`: This function retains the subsequent
initialization tasks including `clock_init()`, `quadspi_init()`,
and `qupv3_fw_init()`.
This change ensures MMU setup to occur before other peripheral and
clock initializations.
TEST=Able to get bootblock console log in proper.
Change-Id: I8bbcdb9c39e13fac81ef6a34647c4f343a619561
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87857
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit adds the `clock_init()` function for the Qualcomm x1p42100
SoC. This function is now called at the beginning of
`bootblock_soc_init()` to enable SoC-specific clock setup early in the
boot process.
The `clock_init()` function definition is currently a placeholder
and will be populated with the required clock configurations in
subsequent changes.
BUG=b:404985109
TEST=Able to build google/bluey
Change-Id: Ifb856ea4132def9cd3a36b081d24037a1a4efaba
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87850
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the fill_tme_params() function to utilize the
CACHE_TMP_RAMTOP constant instead of hardcoded values for calculating
the TME exclusion range.
Change-Id: I199182de8b8b219b0c45b27746b7415527cb9976
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to
access eMMC in the very early stage (for example, depthcharge needs it
20ms after started) so we have to start initialization in coreboot.
BUG=b:379008996
BRANCH=none
TEST=build pass and run "storage init" in depthcharge shell on MTK EVB
firmware-shell: storage init
* 0: mtk_mmc
1 devices total
Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.corp-partner.google.com>
Change-Id: I82f2a155b810a8b9608d70fe0c015e6054d0be00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87862
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The MT8189 chipset comes in two variants: MT8189G and MT8189H. The
MT8189G variant uses a single PMIC IC (MT6315), whereas the MT8189H
variant uses two PMIC ICs. To ensure driver compatibility, we utilize
the CPU ID and segment ID to accurately determine the required number
of SPMIF instances.
BUG=b:379008996
BRANCH=none
TEST=build pass and boot up normally.
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I07bc21a2026803e76861b27a178d229deca2090a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87854
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
In some SoCs, such as MT8189G/H, different numbers of PMICs are
required. To ensure code reusability and compatibility, it is
necessary to dynamically set this variable. Therefore, spmi_dev_cnt
is changed to a function.
BUG=b:379008996
BRANCH=none
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ib8d6306a81c276dceb021ddadec40803fd85019b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87853
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
To support the MTK firmware support package (FSP), reserve a 2MB region
in DRAM for loading `mtk_fsp_ramstage.elf` during ramstage.
BUG=b:379008996
BRANCH=none
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: If153d9746bea8c7faa8f9787029b44192c18899d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87813
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Enables CPU_SUPPORTS_INTEL_TME and TME_KEY_REGENERATION_ON_WARM_BOOT
for Panther Lake, providing hardware memory encryption capabilities.
TEST=Able to build and boot google/francka. Verified TME related
settings inside FSP are now enabled with this patch.
Change-Id: Iedc0d72d00e7e3c5b85916e2de4f020efd5ef024
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit moves the TME configuration into its own static function,
`fill_tme_params`, which is then called from
`fill_fspm_security_params`.
The `TME_KEY_REGENERATION_ON_WARM_BOOT` option is now supported,
allowing a new TME key to be generated on warm reboots.
This feature leverages the `SOC_INTEL_COMMON_BASECODE_RAMTOP`
configuration to determine a memory exclusion range for the new key.
Additionally, disable the `BIOS Guard` UPD as part of security FSP
UPD configuration.
TEST=Able to build and boot google/fatcat. S0ix also works with this
patch.
Change-Id: I1030a25262f1c3c24cf9f4886718689ee2c8155e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87808
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for VMODEM and VSRAM_MD buck converters in MT6359. These
buck converters are required for MT8189 to adjust voltage and CPU
frequency.
BUG=b:379008996
BRANCH=none
TEST=build passed.
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: Ifdf43748a139050ec9fba50f918e071dc622a670
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87799
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Currently on power key long press, PMIC will be reset. It would cause
an unwanted reset pulse in the power-off sequence. To match expected
sequence, change PMIC behavior to "force shutdown".
BUG=b:395848137
BRANCH=none
TEST=long-pressing power key doesn't trigger PMIC_AP_RST_L pulse
Change-Id: Ia8fb9f4a1ffe05955fca51a58468ba338ef8e12d
Signed-off-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch enhances the forced CSE sync mechanism by eliminating the
boot partition check for RO. It uses the persistent CMOS flags to
preserve the forced CSE update status across boots.
This patch also replaces the CSE status boolean variable with a bit
field to optimize CMOS memory utilization. Consequently, the remaining
bits can potentially be utilized for additional CSE states in future.
BUG=b:380220737
TEST=Verified forced CSE sync on google/rex0.
Change-Id: If1e4180cb5fec3990fdee2b0e412173b1c8c6ded
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86153
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Secure System Power Manager (SSPM) provides power control in secure
domain. The initialization flow is to load SSPM firmware to its SRAM
space and then enable it. It takes 19 ms to load sspm.bin.
coreboot logs:
CBFS: Found 'sspm.bin' @0x26740 size 0x645b in mcache @0xfffdd1ec
mtk_init_mcu: Loaded (and reset) sspm.bin in 19 msecs (59392 bytes)
BUG=b:379008996
BRANCH=none
TEST=build pass and see SSPM firmware loading log
Signed-off-by: Hailong Fan <hailong.fan@mediatek.corp-partner.google.com>
Change-Id: I9be0e7ee3d003b5ee9e07e4f136795755a11c5bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87761
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add MCUPM loader for mt8189.
It takes 36 ms to load mcupm.bin.
coreboot logs:
CBFS: Found 'mcupm.bin' @0x10d00 size 0x7fd6 in mcache @0xffffeb20
mtk_init_mcu: Loaded (and reset) mcupm.bin in 36 msecs (84124 bytes)
BUG=b:379008996
BRANCH=none
TEST=build pass and we can see the mcupm logs after reset releases.
Signed-off-by: Justin Yeh <justin.yeh@mediatek.corp-partner.google.com>
Change-Id: I4f3a4eb63d801df123e45f46fc715c39d858c377
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87758
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Enabling MMCONF is simple and should be done first to allow bootblock
code to access the PCI config space. Required to cache ROM3 in
early_cache_setup() that is now called directly after enabling MMCONF.
Change-Id: I5d5f533258985211afafd9bf748f8e26f6128bd4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86619
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On x86_64 use the ROM3 window to access the SPI flash. Use the
same mechanism as on Intel, where the lower 16Mbyte are mapped
using ROM2 window and the upper pages are mapped using the ROM3
window. By default the ROM3 window resides in high MMIO and thus
needs 1024GiB of the address space to be identity mapped in the
page tables.
This allows legacy 32-bit code to work on mappings in the lower
16MiB of the flash chip.
Introduces new messages in coreboot log:
[INFO ] ROM2 Decode Window: SPI flash base=0x0, Host base=0xff000000, Size=0x1000000
[INFO ] ROM3 Decode Window: SPI flash base=0x1000000, Host base=0xfd01000000, Size=0x3000000
TEST: Disabled ROM2 mapping and booted from ROM3 mapping in x86_64
on amd/birman+.
Change-Id: I8976273cfb31765d7f893b3fc137f117c63b6553
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
When the number of eFuse reads exceeds a certain limit (with a maximum
of 20 million), a bit flip from 1 to 0 may happen. When that happens,
the bit flip will be automatically corrected by the eFuse hardware via
ECC (Error Correction Code), and the EFUSE_ECC_ERR register bit will be
set for the software to decide how to handle that.
Therefore, this patch adds a check for the EFUSE_ECC_ERR register bit.
If it's set due to a bit flip instead of a real error, we simply clear
it to avoid triggering a WDT reset.
BUG=b:379008996
BRANCH=none
TEST=build passed and check the WDT status debug log. This log is added
in local for test only.
[INFO ] mtk_wdt_clear_efuse_ecc: wdt_sta = 0x0
Signed-off-by: Zexin Wang <ot_zexin.wang@mediatek.corp-partner.google.com>
Change-Id: Idd2763688c7ab6992a7c185e9e52b60bda88c94c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87744
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Move `post_cpus_init` to execute at the entry of the `BS_DEV_ENABLE`
boot state. This function is responsible for synchronizing
and finalizing MTRR (Memory Type Range Registers) settings across all threads.
This change ensures that MTRR configuration occurs at the correct
point in the boot sequence:
- After main DRAM resources are determined and finalized (typically
by the `BS_DEV_RESERVE_RESOURCES` state). MTRRs define
attributes for these physical memory ranges.
Previously, `post_cpus_init` was hooked at `BS_WRITE_TABLES` (on exit)
or `BS_OS_RESUME` (on entry). Relocating to `BS_DEV_ENABLE` (on entry)
provides a more robust and correctly sequenced execution point for this
essential multi-processor (MP) MTRR setup.
BUG=b:413638298
TEST=Successfully built and booted google/fatcat. Verified that
MTRR programming, which depends on DRAM resource determination
(finalized by BS_DEV_RESERVE_RESOURCES), now correctly
executes at BS_DEV_ENABLE, prior to full device initialization.
Change-Id: I1d2b3f11e4ac268c5b35bf9a8062a77a48a0601a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Update header files for FSP for Panther Lake platform to version
3144_01, with the previous version being 3071_00.
Changes include:
- Update UPD Offset in FspmUpd.h and FspsUpd.h.
- Update MemInfoHob.h:
- Update MEMORY_INFO_DATA_HOB, child structures and their data for
SMBIOS type 16/17 design change.
- Add new variable PprFailingChannelBitMask to
MEMORY_INFO_DATA_HOB.
- Update soc/intel/pantherlake/romstage/romstage.c: Refactor coreboot
to match MEMORY_INFO_DATA_HOB data structure.
BUG=b:414734316
TEST=Able to build google/fatcat. Verify that the updates to
MEMORY_INFO_DATA_HOB and its child structures for SMBIOS type 16/17
design changes are correctly integrated from FSP 3144_01 onwards.
Change-Id: I054e419ef23ada67347750e7a68014c2bb112199
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87000
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
MT8189 equips DPM hardware which is similar to MT8196.
Therefore, we use the same DPM v2 loader to run the blob.
BUG=b:379008996
BRANCH=none
TEST=Make & Boot up pass and see log
mtk_init_mcu: Loaded (and reset) dpm.dm in 19 msecs (1004 bytes)
mtk_init_mcu: Loaded (and reset) dpm.pm in 19 msecs (36588 bytes)
mtk_init_mcu: Loaded (and reset) dpm.dm in 7 msecs (1004 bytes)
mtk_init_mcu: Loaded (and reset) dpm.pm in 19 msecs (36588 bytes)
Signed-off-by: Mike.Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: I616cc0880d2db3f94b2a960b11d04974af1e94ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
MT8196 DPM uses broadcast mode for loading DPM bin files. This means
that both dpm.dm and dpm.pm files only need to be loaded once, and
all channels will apply them.
In contrast, MT8189 DPM uses non-broadcast mode, which requires
loading the dpm.dm and dpm.pm files for each channel individually.
The original dpm_v2.c only supports broadcast mode. In this commit,
add support for non-broadcast mode to increase code reusability.
BUG=b:379008996
BRANCH=none
TEST=build passed.
Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: I599f06c5669f5fd8623966a1c03767ea02b6bd15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87736
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move EC software sync to the SoC code when `VBOOT_EC_SYNC_ESOL` config
is selected. This allows the early Sign-Of-Life (eSOL) to be
displayed during EC firmware update.
`VBOOT_EC_SYNC_SOL` is not coupled with `VBOOT_EARLY_EC_SYNC`,
therefore it can be enabled only for variants whose EC firmware
takes a long time (15-20s) to update.
This change also implements `vboot_show_ec_sync_esol()` function
that displays the eSOL during the update for Alder Lake devices.
AP log during EC firmware update with `VBOOT_EC_SYNC_ESOL` enabled:
```
[INFO ] VB2:check_ec_hash() Heff != Hexp. Schedule update
[0.216229] DP PHY mode status not complete
[0.217189] DP PHY mode status not complete
[INFO ] Informing user on-display of EC software sync.
[DEBUG] FMAP: area COREBOOT found @ c0a000 (4153344 bytes)
[WARN ] CBFS: 'preram_locales' not found.
[INFO ] ux_locales_get_text: preram_locales not found.
[INFO ] VB2:sync_ec() select_rw=RW(active)
[INFO ] VB2:update_ec() Updating RW(active)...
[INFO ] CBFS: Found 'ecrw' @0x1a9f80 size 0x40000 in mcache @0xfef97a9c
[INFO ] VB2:vb2_digest_init() 262144 bytes, hash algo 2, HW acceleration enabled
[INFO ] CBFS: Found 'ecrw.hash' @0x7f8c0 size 0x20 in mcache @0xfef97708
[INFO ] VB2:vb2_digest_init() 32 bytes, hash algo 2, HW acceleration enabled
[INFO ] VB2:check_ec_hash() Hexp RW(active): 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[INFO ] VB2:check_ec_hash() Hmir: 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[WARN ] ec_hash_image: No valid hash (status=0 size=0). Computing...
[INFO ] EC took 482169us to calculate image hash
[INFO ] VB2:check_ec_hash() Heff RW(active): 62d1d55d26f33bd01a3676656148bedacf44189c81b195ec5488499074fe9bb0
[INFO ] VB2:update_ec() Updated RW(active) successfully
[INFO ] VB2:sync_ec() Rebooting to jump to new EC-RW
[INFO ] VB2:vb2api_ec_sync() ec_sync_phase2(ctx) returned 0x1004
[INFO ] EC Reboot requested. Doing cold reboot
```
BUG=b:412210635
TEST=Verify successful EC sync in romstage. Verify eSOL is displayed
during EC update on a nissa (Alder Lake) board by enabling
`VBOOT_EC_SYNC_ESOL` config.
Change-Id: I351d464f2ca64a3e60c52f88c8633e05556c5324
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87670
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the MT6359 datasheet, set the RTC EOSC calibration period
to 8 seconds to ensure that the power source VXO22 in the MT6359 meets
the expected power sequence in AP power-off mode.
BUG=b:397292746
BRANCH=none
TEST=build pass & boot pass
Change-Id: I4043f4e82baeb8e0358e74dd6d088895e4deb0f4
Signed-off-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87705
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
To promote code reuse and maintainability, move mt8196/sspm_sram.c to
common folder. The macro for the register SSPM_SRAM_CON is replaced by
'mtk_spm->sspm_sram_con' since it is already defined in spm.h.
BUG=b:379008996
BRANCH=none
TEST=build passed.
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I71912a23537a8bb26ed431d06123a875b80b8e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87661
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Move function declarations to dpm_common.h, which is shared for both
dpm_v1 and dpm_v2. Add a new function dpm_init_mcu() to the header to
reduce duplicate code in dpm_v1.c, dpm_v2.c and dpm_4ch.c.
BUG=none
TEST=emerge-skywalker coreboot
BRANCH=none
Change-Id: I8d6318e9c3c4570cb8f3ff64242fc414770db653
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
When using the CFR option backend, a mainboard may want to set the ME
default state to disabled, so add a Kconfig which can be selected to do
so.
Change-Id: I53d88af5e5cc9b7300b847e4aaf8e4cd2ce5bb75
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87649
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: I572f119c86ea0e2a16d4bb543bc61afab423d092
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.
Change-Id: I2d02184c82ef4874518a3f8e1fe0f5a195188f2a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: I083cd4dfc5d4ee7807345c423872d27b66c4edc1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87631
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.
Change-Id: Ib964e4c2779fe467086681f55136237a69a8f736
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: I08d7c39ba9be92d6a267d20068f41980a5042755
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.
Change-Id: Ifa0b567c05e48c4f0f5dc2fc385cf5f82eb083a0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.
Change-Id: I728b71826798eb94c13e54aeadd3ca69c2bf5e8f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87626
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add enums for the IGD aperture size and DVMT/stolen memory size, as is
done for newer SoCs. Use these enums rather than their int values
when configuring the IGD.
Change-Id: I369f9c73a00b41b056c89975d4c7e643f1e900c1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87625
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add enums for the IGD aperture size and DVMT/stolen memory size, as is
done for newer SoCs. Use these enums rather than their int values
when configuring the IGD.
Change-Id: I16dbfcd1862ea0c43c62eef59e35ca144a1b2715
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87624
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the IGD UPDs for configuring the DVMT allocated memory and
the aperture size to the option API, so they can be configured via
CMOS/CFR. Default values are set to existing values if option API
is not used.
Add enums to map the DVMT and aperture size UPD values to user-
friendly ones, as was previously done for other SoCs.
Change-Id: Id85e698263b0193d0a83cd4d6ee6c10c89a1d2fa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87623
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the IGD UPD for configuring the DVMT allocated memory to the
option API, so it can be configured via CMOS/CFR. Default value is set
to the existing fixed value of 128MB if option API is not used.
Change-Id: I413e958e3c02632c3920b39dd370b89ecc99613f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
