0baf47e03b
Update header files for FSP for Panther Lake platform to version
3144_01, with the previous version being 3071_00.
Changes include:
- Update UPD Offset in FspmUpd.h and FspsUpd.h.
- Update MemInfoHob.h:
- Update MEMORY_INFO_DATA_HOB, child structures and their data for
SMBIOS type 16/17 design change.
- Add new variable PprFailingChannelBitMask to
MEMORY_INFO_DATA_HOB.
- Update soc/intel/pantherlake/romstage/romstage.c: Refactor coreboot
to match MEMORY_INFO_DATA_HOB data structure.
BUG=b:414734316
TEST=Able to build google/fatcat. Verify that the updates to
MEMORY_INFO_DATA_HOB and its child structures for SMBIOS type 16/17
design changes are correctly integrated from FSP 3144_01 onwards.
Change-Id: I054e419ef23ada67347750e7a68014c2bb112199
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87000
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
||
|---|---|---|
| .. | ||
| amd | ||
| cavium | ||
| example/min86 | ||
| ibm/power9 | ||
| intel | ||
| mediatek | ||
| nvidia | ||
| qualcomm | ||
| rockchip | ||
| samsung | ||
| sifive | ||
| ti | ||
| ucb/riscv | ||
| xilinx | ||