soc/mediatek/common: Add DPM V2 non-broadcast mode support

MT8196 DPM uses broadcast mode for loading DPM bin files. This means
that both dpm.dm and dpm.pm files only need to be loaded once, and
all channels will apply them.

In contrast, MT8189 DPM uses non-broadcast mode, which requires
loading the dpm.dm and dpm.pm files for each channel individually.

The original dpm_v2.c only supports broadcast mode. In this commit,
add support for non-broadcast mode to increase code reusability.

BUG=b:379008996
BRANCH=none
TEST=build passed.

Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: I599f06c5669f5fd8623966a1c03767ea02b6bd15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87736
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/mediatek/common/Kconfig

@@ -67,6 +67,12 @@ config DPM_FOUR_CHANNEL
 	help
 	  This option enables four channel configuration for DPM.
 
+config DPM_BROADCAST
+	bool
+	default n
+	help
+	  This option enables the DPM Broadcast function, applicable only for dpm_v2.
+
 config MTK_DFD
 	bool "Enable MediaTek DFD (Design For Debug) settings"
 	help

src/soc/mediatek/common/dpm_v1.c

@@ -4,6 +4,9 @@
 #include <soc/dpm_v1.h>
 #include <soc/mcu_common.h>
 
+_Static_assert(!CONFIG(DPM_BROADCAST),
+	       "DPM_BROADCAST not implemented in dpm_v1");
+
 static struct mtk_mcu dpm_mcu[] = {
 	{
 		.firmware_name = CONFIG_DPM_DM_FIRMWARE,

src/soc/mediatek/common/dpm_v2.c

@@ -4,14 +4,34 @@
 #include <soc/dpm_v2.h>
 #include <soc/mcu_common.h>
 
-static struct mtk_mcu dpm_mcu[] = {
+_Static_assert(!CONFIG(DPM_FOUR_CHANNEL),
+	       "DPM_FOUR_CHANNEL not implemented in dpm_v2");
+
+static struct mtk_mcu dpm_mcu_ch0[] = {
 	{
 		.firmware_name = CONFIG_DPM_DM_FIRMWARE,
 		.run_address = (void *)DPM_DM_SRAM_BASE,
+		.priv = (void *)DPM_CFG_CH0,
 	},
 	{
 		.firmware_name = CONFIG_DPM_PM_FIRMWARE,
 		.run_address = (void *)DPM_PM_SRAM_BASE,
+		.priv = (void *)DPM_CFG_CH0,
+		.reset = dpm_reset,
+	},
+	{},
+};
+
+static struct mtk_mcu dpm_mcu_ch1[] = {
+	{
+		.firmware_name = CONFIG_DPM_DM_FIRMWARE,
+		.run_address = (void *)DPM_DM_SRAM_BASE2,
+		.priv = (void *)DPM_CFG_CH1,
+	},
+	{
+		.firmware_name = CONFIG_DPM_PM_FIRMWARE,
+		.run_address = (void *)DPM_PM_SRAM_BASE2,
+		.priv = (void *)DPM_CFG_CH1,
 		.reset = dpm_reset,
 	},
 	{},
@@ -19,20 +39,30 @@ static struct mtk_mcu dpm_mcu[] = {
 
 void dpm_reset(struct mtk_mcu *mcu)
 {
+	uintptr_t dpm_cfg_reg = (uintptr_t)(mcu->priv);
 	/* free RST */
-	setbits32p(DPM_CFG_CH0 + DPM_RST_OFFSET, DPM_SW_RSTN);
+	setbits32p(dpm_cfg_reg + DPM_RST_OFFSET, DPM_SW_RSTN);
 }
 
 int dpm_init(void)
 {
-	u32 dramc_wbr_backup = read32p(DRAMC_WBR);
+	u32 dramc_wbr_backup;
 
-	setbits32p(DRAMC_WBR, ENABLE_DRAMC_WBR_MASK);
+	if (CONFIG(DPM_BROADCAST)) {
+		dramc_wbr_backup = read32p(DRAMC_WBR);
+		setbits32p(DRAMC_WBR, ENABLE_DRAMC_WBR_MASK);
+	}
 
-	if (dpm_init_mcu(dpm_mcu))
+	if (dpm_init_mcu(dpm_mcu_ch0))
 		return -1;
 
-	write32p(DRAMC_WBR, dramc_wbr_backup);
+	if (!CONFIG(DPM_BROADCAST)) {
+		if (dpm_init_mcu(dpm_mcu_ch1))
+			return -1;
+	}
+
+	if (CONFIG(DPM_BROADCAST))
+		write32p(DRAMC_WBR, dramc_wbr_backup);
 
 	return 0;
 }

src/soc/mediatek/common/include/soc/dpm_v2.h

@@ -10,6 +10,7 @@
 #define DPM_SW_RSTN		BIT(0)
 
 #define DPM_CFG_CH0		DPM_CFG_BASE
+#define DPM_CFG_CH1		DPM_CFG_BASE2
 #define DPM_BARGS_CH0_REG0	(DPM_CFG_BASE + 0x6004)
 #define DPM_BARGS_CH0_REG1	(DPM_CFG_BASE + 0x6008)
 #define DRAMC_WBR		(INFRACFG_AO_BASE + 0x0b4)

src/soc/mediatek/mt8196/Kconfig

@@ -13,6 +13,7 @@ config SOC_MEDIATEK_MT8196
 	select MEDIATEK_DRAM_BLOB_FAST_INIT
 	select USE_CBMEM_DRAM_INFO
 	select SOC_MEDIATEK_COMMON
+	select DPM_BROADCAST
 	select FLASH_DUAL_IO_READ
 	select ARM64_USE_ARCH_TIMER
 	select PCI