Move the programming of the power state after power failure to the ITE
EC common code, in order to unify and extend to other ITE SIO chips.
The implementations in the it8720f and it8728f are functionally
identical, so take the "best" style elements of both, using clear
variable names and defines for registers rather than magic values.
Change-Id: I4b7e9455e964320f35997fdf04a515b942e030c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: I734262c8191bc217c721c0174d0f844755bc73a9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79918
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: I2f7e3e1dc6b3d8d6159bd4701e6fd90f4b0f67f4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79917
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the epic variant of the nissa reference board by copying
the template files to a new directory named for the variant.
This variant is a Nirul project,support TWL devices and select
BOARD_GOOGLE_BASEBOARD_NISSA.
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H58G56AK6BX069 1 (0001)
K3LKBKB0BM-MGCP 2 (0010)
H9JCNNNBK3MLYR-N6E 0 (0000)
H9JCNNNCP3MLYR-N6E 3 (0011)
BUG=404301972
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_EPIC
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I09e5f3c28b95ae8ef318b7af1dd8634279345ce0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87041
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
With DRIVERS_EFI_UPDATE_CAPSULES enabled and when at least one capsule
was found, SMMSTORE SMI handler can use commands with the highest
bit (0x80) set to access the whole flash instead of just the SMMSTORE
region. The rest of the interface is identical to regular SMMSTORE v2
except for a new call to control full flash access.
The added call saves information about the availability of capsules in
SMM memory. The call is ignored when run more than once, meaning there
should be no way of enabling full flash handling after it was disabled
and vice versa. The call should always be made by the firmware to lock
further calls, so that an OS could not gain full flash access. This is
done on entry to BS_POST_DEVICE after capsules are obtained in
BS_DEV_INIT.
Change-Id: I7f3dbfa965b9dcbade8b2f06a5bd2ac1345c7972
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This reverts commit 2fdfa50437.
Reason for revert: libbl31.a is under refactoring. Stop linking to this
library before finalizing the binary. This patch will be re-landed when
the binary is ready.
BUG=b:412560091
Change-Id: Ie2c315141a51f30027414cfe59552cb50f2b52f6
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87414
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use GPP_C08 as the GPIO_PCH_WP.
BUG=b:409472563
Test=TEST=wp status update verified by toggling it on and off.
Change-Id: I0f6c7c051b2d38a787fe3bb21266a6ef6ebc487b
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87413
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Two ME current working state definitions are missing. They are
needed for CB:85413. Get them from intelmetool.
Change-Id: Ie163c4b29155e3fd44f0cb3096f825c84da37559
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87394
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- some formatting fixes;
- add information about proprietary blobs;
- update information about the tested hardware and operating systems.
Change-Id: I85a8f1df2ffc6e0e1674c4b82888a3964aa8d672
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The memory dump was done for the 1.80 (2023-04-07) version of the
vendor's UEFI.
Change-Id: I649e2c3ae715651b5f0eadc9b52e61e4deae77a1
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
It's an ACPI spec violation for a device to have both an _ADR and
a _HID method, so prefer the latter if a HID value is specified
via the chip registers.
Change-Id: I5d84dbea52595e61df56a5ff779d5e0ee0d84bdf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87248
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On SoCs like Glinda, CPU cores may exhibit slight variations in
maximum boost frequency, and the L3 cache can be composed of
multiple blocks with different sizes and unique IDs.
Add helper functions,
1. get_max_boost_frequency() to compute max boost frequenncy.
2. ap_stash_core_info() to update core_info struct with max boost
frequency & all L3 cache block uniq ID & its size.
To accurately determine the total L3 cache size:
1. Retrieve L3 cache information for each CPU core.
2. Identify the unique cache ID associated with each core.
3. Aggregate cache sizes for all unique cache IDs to compute the
total L3 cache size, ensuring correct summation when L3 cache
blocks have different sizes.
TEST=Build for Glinda SoC, with L3 cache = 16MB + 8MB. Ran command
'dmidecode -t 7' & verified L3 cache is 24MB(Previously it was
wrongly reported as 32MB).
Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85640
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the interrupts coming from the sensors into the ISH.
BUG=b:410645679
Change-Id: I2acaed1900e248cfe7fcc81201c6991a9741f26c
Signed-off-by: Yuval Peress <peress@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87333
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the kinmen variant of the fatcat reference board by copying
the fatcat files to a new directory named for the variant.
BUG=b:409148565
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_KINMEN
2. Run part_id_gen tool without any errors
Change-Id: I51e388e61f102216f6ce9233c87c1915596602be
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87317
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Control ISH device and corresponding GPIOs using a FW_CONFIG field.
BUG=b:410645679
TEST=Enable/Disable ISH using the new FW_CONFIG field.
Change-Id: I69805116722535d77c7fd7701df261e0faa9138f
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Yuval Peress <peress@google.com>
Add a DSD with the HotPlugSupportInD3, as when it RTD3, the device
will appear as not-present. This will cause Windows to constantly
try to enable it, causing an endless loop of the device becoming
visible.
Test=build and boot `starlabs/starlite_adl`, check CNVi is always
visible in device manager.
Change-Id: I598ab173074522e9d5af002782c5d3ec7691a815
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87325
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a DSD with the HotPlugSupportInD3, as when it RTD3, the device
will appear as not-present. This will cause Windows to constantly
try to enable it, causing an endless loop of the device becoming
visible.
Test=build and boot `starlabs/starlite_adl`, check Bluetooth is
always visible in device manager.
Change-Id: I51a2c764ebe8b98b137eb0c98cfdcf2de6f4b86c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87324
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The previous implementation used _PS0 and _PS3 methods to control the
device power states. These are now replaced by a _S0W object to better
align with both coreboot's existing RTD3 driver, and the examples in
the ACPI specification.
This ensures that the Bluetooth device is recognized as capable of
reaching D3Hot when the system is in S0.
Test=build and boot starlite_adl with Windows and Linux, check Bluetooth
is functional and power draw decreases ~0.4W with no devices connected.
Change-Id: I6762b4a2a2454d4e4de2b25e3e5db17df5a8fc63
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The previous implementation used _PS0 and _PS3 methods to control the
device power states. These are now replaced by a _S0W object to better
align with both coreboot's existing RTD3 driver, and the examples in
the ACPI specification.
This ensures that the Bluetooth device is recognized as capable of
reaching D3Hot when the system is in S0.
Test=build and boot starlite_adl with Windows and Linux, check Bluetooth
is functional and power draw decreases ~0.4W with no devices connected.
Change-Id: I8aa49ee2220ba2ea39b343ea9a9486fca9f5f3d5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87241
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a check in the _ON method, similar to coreboot's ONSK handling
in its RTD3 driver, to determine whether the enable GPIO is already
asserted.
This prevents the OS from repeatedly invoking _ON, which can happen
because CNVi takes around 300ms to initialize after the GPIO is
enabled.
Change-Id: I53986aa11714666c12056460aa47396266a00a1c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add a check in the _ON method, similar to coreboot's ONSK handling
in its RTD3 driver, to determine whether the enable GPIO is already
asserted.
This prevents the OS from repeatedly invoking _ON, which can happen
because USB Bluetooth takes around 200ms to initialize after the
GPIO is enabled.
Change-Id: I424bc5f4c5b990fd5cb54daa3d6207828386c6f2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87239
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Guarding the existence of this register isn't necessary since we
guard its usage as well, and it complicates some subsequent changes,
so drop it.
Change-Id: I557c400e6dffeb9dc5b4b67a6cc6f15ba0ef27d0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87343
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The definitions were reversed, as PCH_S should use 0x44, and all others
0x80.
These values can be seen in SlimBootloader, and most UEFI firmwares.
Change-Id: Ia2e3866ef7d0756220f15a8d2bdf639ac6667738
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87323
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Similarly to how things are done for the I2C controller configuration,
implement the 'soc_get_i3c_ctrlr_info' function in all SoCs that have
I3C controllers. This function returns the contents of the SoC's
'i3c_ctrlr' array containing the base addresses and ACPI names of the
I3C controllers. This function will eventually be called by the common
I3C code which will be implemented in future patches.
Change-Id: Ib23fd896925770f49e567324bc8d12ac4c0944bd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87280
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These GPIOs are not used, so configure them accordingly.
Change-Id: I4e58a0e7545167db2c4034499bb99d3bfffc2277
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87164
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.
Set these all to sample on RSMRST.
Change-Id: I3f7133666743b8aa0dc39df54ffe3483a1ddd605
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87162
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that we require the FMAP to start at offset 0 in the flash, we can
assume this across the entire codebase and therefore simplify it on
several ends.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ieb1a23f9c0ae8c0e1c91287d7eb6f7f0abbf0c2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86771
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
For simplicity we are going to impose this restriction to coreboot.
Note however that this is only a restriction for coreboot itself. The
FMAP tool itself is still a generic tool that does not require the FMAP
to start at offset 0.
Add an defacto empty fmap_config.h to our test cases, since fmap.h now
includes fmap_config.h.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iba04ebdcd5557664a865d2854028dd811f052249
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Duty Cycle Correlation (DCC) analyzes and optimizes the relationship
between the duty cycles of multiple signals. This commit implements DCC
driver support to improve clock signals, power management, and
communication systems, enhancing system stability and performance.
These improvements will become more significant as the SoC ages.
BUG=b:389784352
BRANCH=rauru
TEST=Build pass, check dcc log:
[DEBUG] [DCC] DSU=0x0, LCPU=0x0, MCPU=0x17, BCPU=0x1b
Change-Id: I77e5cd951f45dad7a6e2e77c135b821e4179e019
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87320
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Make mt6359p_read_field() a general API usable by multiple drivers,
instead of a static function limited to the original driver.
BUG=b:379008996
BRANCH=none
TEST=build pass
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I2d9c3de9ad08f918a84fa63c1e9b3af7adc5974a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87336
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
We have to reset the USB hub as early as possible. Otherwise the USB3
hub may not be usable in the payload. This design has been introduced
since Cherry.
BUG=b:390357201
BRANCH=none
TEST=detect USB devices in depthcharge, and the log is like "Added USB
disk 2."
Change-Id: I4ee24aef2a887c8a30738912a8bf90f830a72bed
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87348
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Configure GPIO (XHCI_INIT_DONE) as output, so that payloads (for example
depthcharge) can assert it to notify EC to enable USB VBUS.
BUG=b:390357201
BRANCH=none
TEST=detect USB devices in depthcharge, and the log is like "Added USB
disk 2."
Change-Id: I99760ace3e87626f55c52dc4f8a30bab27cba345
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Since infracfg.h is not used in pmif_spi.c, remove its inclusion to
prevent build errors in projects that don't have infracfg.h.
BUG=b:379008996
BRANCH=none
TEST=build pass
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I09229ff370a53407b3f0c290704887de367ed80b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87339
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The flickering issue on ATNA40HQ01-0 panel can be resolved by setting
the swing level to the maximum (500mV). Therefore, add FORCE_MAX_SWING
quirk for ATNA40HQ01-0 panel where the fw config's OLED_WQXGA_PLUS field
is set to PRESENT. As OLED_WQXGA_PLUS is currently only available on
Navi, add an overridetree.cb for Navi.
BRANCH=rauru
BUG=b:392040003
TEST=check edp training pass and show log:
[INFO ] fw_config match found: OLED_WQXGA_PLUS=PRESENT
...
[INFO ] update_swing_preemphasis: Force swing setting to 3 (500 mV)
Change-Id: I4797ef8fe2257a9b578a969794d624d6e0f97d07
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87028
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
