Mainboard family is set based on the baseboard.
TEST=build/boot google/galtic, verify mainboard family set correctly
in SMBIOS.
Change-Id: Ifb5335c7dad43e8a75dd462a121d2eb711c51ccc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89453
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These boards all use PDM1 for the microphone topology, and so need to
override the baseboard default.
TEST=boot Win11 on omnigul, verify speakers/microphone work with
Coolstar's drivers.
Change-Id: I55a5886fc02a83640392854cd7132aa811dac6f3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89454
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for taking the ifdtool platform parameter via the cmd
line, as well as the output directory. Add double quotes around
variables as needed. Add help output describing new parameter options.
TEST=run script against images from skl, adl, and mtl platforms.
Verify no warning from ifdtool that platform is unknown.
Change-Id: I4a27c9876bf639579b791c894b2cbfdae7ab63c1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Introduce a Kconfig option EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC for
reading firmware configuration from Unified Firmware and Second-source
Config (UFSC) [1] from EC CBI. As the UFSC already includes both the
32-bit FW_CONFIG and 32-bit SSFC, this option is incompatible with
EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG.
Also check the size of the data read from CBI.
[1] https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/6974727
BUG=b:448300592
TEST=emerge=skywalker coreboot
BRANCH=none
Change-Id: I2f686838d2f7a6f3eec3bd5224f89389340f7471
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89404
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The changes focus on offering power state current thresholds and Thermal
Design Current (TDC) mode settings.
The Ps1Threshold, Ps2Threshold, and Ps3Threshold new fields configure
current thresholds for different power states. This allows for
fine-tuned power management by specifying current thresholds in 1/4 A
increments. These configurations can help optimize performance based on
specific current requirements for different components like IA, GT, and
SA.
The TdcMode parameter configures TDC mode based on the IRMS supported
bit from Mailbox, offering the option between iPL2 and Irms modes.
BUG=b:449662274
Change-Id: I25b6b9d2bf19ade51e39db06298ffaef98a7897e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88043
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors the MMU configuration for the DMA region by moving
the logic from mmu_cmops.c to the common/mmu_operations.c. This
centralization simplifies the code and removes duplication.
The following changes are included:
- Deleted src/soc/mediatek/common/mmu_cmops.c
- Moved DMA region configuration to mtk_mmu_after_dram
- Updated Makefiles to remove references to the deleted file
BRANCH=none
BUG=none
TEST=emerge-kukui coreboot -j && emerge-elm coreboot -j && \
emerge-rauru coreboot -j
Change-Id: I06289afa74248d55fc1eabeef2f6591bc805a8cf
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89411
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The macros being removed are already defined in the soc/memlayout.h.
Remove the duplicated definitions and include the common header instead.
BUG=none
TEST=emerge-asurada coreboot
Change-Id: I38d9ca2310fbc60bb453b9731203ffb0251cb444
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89410
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change refactors `configure_backlight` function to accept a boolean
'enable' parameter. This provides more explicit control over the
backlight state.
BUG=b:319511268,b:319511268
TEST=emerge-rauru coreboot
Change-Id: Ia713dc792186a9a8080fd9d7ee02738fd372f531
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The E6400 and E7240 were updated to use a variant scheme in commit
f62734976c ("mb/dell: Convert E6400 into a variant") and commit
511872dae3 ("mb/dell: Convert Latitude E7240 into a variant"),
respectively, which changed the names of the directories they were
located in. Update MAINTAINERS to reflect this.
Change-Id: If35e5a0afe214fe623334e90969cc7f95d579a86
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Options are organized to be as close to vendor firmware as possible.
Some options are not implemented for all variants. Those are either
excluded from build via preprocessor, or left visible but unused.
They will be squared off later.
TEST=abuild tested on the whole series.
TEST=Complete platform setup menu appears for mb/asus/p8z77-v_le_plus
with edk2/mrchromebox payload, with changes to front audio panel type
reflected in hardware.
Change-Id: I558012b28d098a90863e3ff6610017c2410c23ed
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Because the name NINJA has 2 occurrences inside remote recovery.conf:
https://dl.google.com/dl/edgedl/chromeos/recovery/recovery.conf
Running 'crosfirmware.sh ninja' will list both NINJA and VORTININJA
"file= & url=" with a total of 4 lines instead of 2. Since the script
by default uses the last 2 lines it will prefer VORTININJA and download
the Octopus MEEP recovery image instead while NINJA was requested.
By adjusting 'grep' its matching control by adding '-w' restores the
correct behaviour of only showing 2 lines for the requested image.
Both NINJA, VORTININJA and a third recovery image TIDUS still download
and extract correctly when applying this fix.
TEST=crosfirmware.sh ninja #downloads and extract correct image
Change-Id: I9b55c5a2626339e70f0ada9b80c9488a5580d371
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Align DDR and IMEM address definitions with memory layout
specifications. Modify CBMEM top address accordingly.
Changes include:
- Declaring new memory regions in symbols_common.h.
- Defining base addresses and sizes for these regions in memlayout.ld.
- Marking these regions as reserved in soc_read_resources() to
prevent overwrites by coreboot.
- Modifying CBMEM top address.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I77c95198d6e42635ab7ecaac41fbd29133cb0fa0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89348
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Devices utilizing the second SKU of the SoC experience system hangs due
to missing DVFS support. This patch adds DVFS support for the second
SKU to resolve this issue.
BRANCH=rauru
BUG=b:443664123
TEST=verify booting on both original and second SoC SKUs
Change-Id: If17ecd4a8358e08a45c4662bb92138b7a939512e
Signed-off-by: Jason Chen <jason-ch.chen@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89405
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: jason-ch chen <Jason-ch.Chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was supposed to be checked in the regression test script
(CB:88763), however it turns out Valgrind's Memcheck only works on the
heap memory and is unable to catch such errors.
The regression test script was modified to use AddressSanitizer which
can catch such errors, so this should not be a problem in subsequent
changes during the verb table rework.
To be safe, the previously merged commits were also checked with the new
regression test script:
f634121fa4 ("mb/purism: Replace verb tables with reworked implementation")
20d4042458 ("mb/asrock: Replace verb tables with reworked implementation")
2b7dbf80c9 ("mb/apple: Replace verb tables with reworked implementation")
970249694f ("mb/amd: Replace verb tables with reworked implementation")
94beaa7ab3 ("mb/acer: Replace verb tables with reworked implementation")
f3db3a19d5 ("mb/51nb: Replace verb tables with reworked implementation")
However, the following mini-HD code was checked manually, as figuring
out how to strip out minihd_init() was not worth the effort:
bc92d9a666 ("nb/intel/haswell/minihd.c: Add reworked verb table implementation")
69781b9806 ("soc/intel/broadwell/minihd.c: Add reworked verb table implementation")
Change-Id: Iea964fb8b92814b57d4c82412c47cf31fa48de66
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89376
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some boards did not provide the chip name for the audio codecs in the
comments, and were therefore identified using external sources:
h61m-a_usb3:
- 0x10ec0887 -> Realtek ALC887[1][5]
h61m-cs:
- 0x10ec0887 -> Realtek ALC887[1][6]
p8h61-m_pro:
- 0x10ec0887 -> Realtek ALC887-VD[3]
p8h67-i_deluxe:
- 0x10ec0892 -> Realtek ALC892[3][7]
p5gc-mx:
- 0x10ec0892 -> Realtek ALC662[2]
p5qc:
- 0x10ec0888 -> Realtek ALC1200[2]
p5ql-em:
- 0x10ec0888 -> Realtek ALC1200[8]
p8z77-m:
- 0x10ec0887 -> Realtek ALC887[1][9]
p8z77-v:
- 0x10ec0892 -> Realtek ALC892[3][10]
p8z77-v_le_plus:
- 0x10ec0889 -> Realtek ALC889[4][11]
The Kconfigs were reverted using the following command:
find src/mainboard/asus -name 'Kconfig' | xargs git checkout main
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see commit 31fc5b06a6
("device: Introduce reworked azalia verb table").
References:
[1] Linux kernel: sound/hda/codecs/realtek/alc882.c:839
[2] coreboot board status: kernel_log.txt
[3] Linux kernel: sound/hda/codecs/realtek/alc662.c:1101
[4] Linux kernel: sound/hda/codecs/realtek/alc882.c:842
[5] H61M-A/USB3 User's Manual (English), Version E8184
[6] H61M-CS User's Manual (English), Version E9069
[7] P8H67-I Deluxe User's Manual (English), Version E6964
[8] P5QL-EM user’s manual(English), Version E4165
[9] P8Z77-M User's Manual (English), Version E7075
[10] P8Z77-V User's Manual (English), Version E7074
[11] P8Z77-V LE PLUS User's Manual (English), Version E8001
TEST= All boards passed regression test (CB:88763)
Change-Id: Id2d4895bb40885f83d602b3a80805a84e348771b
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
This board uses PCI to send POST codes to the NC FPGA. Enable the
feature of sending the POST codes to the NC FPGA via PCI so that the
POST codes are visible in coreboot.
TEST=Built and booted on mc_rpl1. Check that the POST Codes are
correctly displayed on the 7-segment display.
Change-Id: I95a1ac7121560b812aea36485c37f39e13de535a
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
All mc_rpl boards have, like the mc_apl and mc_ehl variants, legacy
PCI devices which take longer to boot. To ensure their correct
enumeration, a delay is added before the PCI scan starts. The delay
value is provided by hwinfo.
TEST=Built and booted on mc_rpl board. Verified legacy PCI devices
enumerate correctly after delay implementation. Log excerpt while
testing function:
```
[INFO ] tlcl2_extend: response is 0x0
[DEBUG] TPM: Digest of `CBFS: hwinfo.hex` to PCR 3 measured
[NOTE ] Wait remaining 6595702 of 10000000 us for legacy devices...done!
[DEBUG] BS: BS_DEV_ENUMERATE entry times (exec / console): 6597 / 64 ms
[INFO ] Enumerating buses...
```
Change-Id: I97885a7cf060bc69c7fef75a9fa917bc8a176582
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89393
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Commit 266041f0e6 ("console: Add compile-time fast path when only
CBMEM console is used") introduced a typo when refactoring CBMEM console
fast path code that effectively causes consoles to never get flushed.
The fact that nobody complained in 3 years shows that the flush callback
is probably not that important for most consoles in practice. Still,
it's a pretty bad bug and should be fixed.
Change-Id: Ib9b96cb744447ccba99c4186540442b542914e01
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89397
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This updates the statistics for actual release tag.
Change-Id: I84116caa35be2df28372dd4293ad73eb13ec9dd4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Macros are generated using the hda-decoder utility.
TEST: update coreboot in ROM with this patch -> boot Ubuntu 24.04 again
-> the hda-decoder output before and after the update are the same
and the audio works.
Change-Id: I33d693a483c43a31d6dbb75a97b3ca5f5149fd69
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89371
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
coreboot 24.12, 24.08, and 4.21 have already been released, so the
"Upcoming release" text in their titles is outdated and unnecessary.
Change-Id: I19cb5585c838c64366e057ceeaf0a18e01372bfe
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Configure GPP_F10, GPP_F11, GPP_F12, GPP_F13, GPP_F16, and GPP_F17
as no-connects by default. These GPIOs will be enabled in
fw_config.c if they are needed.
BUG=b:447648103
TEST='emerge-ocelot coreboot chromeos-bootimage`, flash and boot ocelot
and verify the AUDIO_ALC721_SNDW still works.
Change-Id: I7c07581e2b29bfc3e83314a065fba7d418e07c2a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit refactors the handling of CPU IDs for the Pantherlake and
Wildcat Lake series by using a single CPU ID mask instead of listing
each individual stepping. This change simplifies the code by reducing
redundancy and making it easier to manage CPU IDs.
Previously, each stepping of the Pantherlake series had its own entry,
which led to unnecessary complexity. By consolidating these into a
single entry with a mask, we improve maintainability and reduce
potential errors.
These modifications do not affect the existing functionality but
streamline the codebase for future updates and maintenance.
TEST=CPU ID c06c1 is properly identified as "Pantherlake".
Change-Id: Ie52ed860c096a3d157ae6580aeedf3acb8c723ab
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89375
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DPTF parameters were defined by the thermal team.
Based on thermal table in b:448253910 comment#1
BUG=b:448253910
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I91ad12bdb58432b3c2b867278ec5b396553ac2b9
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89380
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add enums for the output pin widget node IDs for Realtek ALC887 [1] and
use these enums in the motherboard configuration.
[1] Figure 1, Block Diagram, ALC887-GR Datasheet, Rev. 1.0, 24 July 2008
Change-Id: Iaa2ebd7447a19dfc98b006c851f1605851c1ea5d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Because we use dummy ish in pujjoquince, so disable ish related gpio
when fw_config TABLET_MODE=TABLET_MODE_DISABLE
BUG=b:432649211
TEST=Build and boot to OS, check pujjoquince ish related gpio are closed.
Change-Id: Iab43f6d4ce3a6d31358ac0b902535ee3f5dad1e3
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
In 76e0f64035, it overrides
GPIO_PCH_WP in variant/gpio.h, however gpio.c includes
baseboard/gpio.h instead of variant/gpio.h. The wrong GPIO header
causes the test firmware.WriteProtectCrossystem to fail with the
wrong GPIO_PCH_WP pin number. Corrects the header file included in
gpio.c to fix the issue.
BUG=b:448313028
TEST=Pass firmware.WriteProtectCrossystem
Change-Id: I94b2384d03f8ce83f662a2b9dba4039f3d551b07
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89389
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 1e7908fa9f ("mb/google/skywalker: Set up all output GPIOs") set
up all output GPIOs to the desired initial value. However, as the
GPIO_USB3_HUB_RST_L pin is already pulled high in usb3_hub_reset() right
before the setup_chromeos_gpios() call, we should not pull it low again.
Otherwise all the USB3 hubs would stop working.
Fix the issue by moving the configuration from usb3_hub_reset() to
setup_chromeos_gpios(), where GPIO_USB3_HUB_RST_L is pull high to reset
USB3 hub.
BUG=none
TEST=emerge-skywalker coreboot
TEST=USB3 hub working properly during bootup
BRANCH=skywalker
Change-Id: Id53ddb033166f7fdcf6b5fc50b538ee29d5d85bb
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89388
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure PWR_EN and RST GPIO of fingerprint sensor.
BUG=b:438785495
TEST='emerge-fatcat coreboot' and boot into os,
fingerprint function is ok.
Change-Id: If896fa5c0600c4bef9ea2c67a30205bcf2689bd1
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89305
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This moves most of the vendor and architecture independent code into
common ACPI code.
Change-Id: I7dca939612a5f3d8d6a148fa67bf0ce891952584
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88034
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The commit addresses an issue with discrete WIFI driver configuration
under root port 4 in the Intel PtlRvp mainboard. The problem involved
incorrect probe settings that allowed the WIFI driver device to remain
enabled even when its upstream device was disabled. This led to orphan
devices being misidentified as root devices within the Intel Power
Engine (PEP) structure, which in turn caused unnecessary MCHC devices
to be added under the root port.
The fix involves ensuring that the probe settings for the devices
managed by the driver are consistent with their upstream device
settings. Additionally, the RTD3 driver device type is now set to
generic, ensuring that only one PCI device exists under the root port.
This prevents the binding of device operations (ops) for the RTD3 driver
from interfering with the WIFI generic driver during the scan process.
The commit also resolves warnings related to leftover static devices and
prompts to check the devicetree.cb. The fix ensures that the probe
settings for WIFI_PCIE_6 and WIFI_PCIE_7 are properly configured,
preventing device misidentification and ensuring correct functionality.
BUG=none
TEST=Boot to OS and verify the DSDT tables. Ensure the _DSM function of
the PEPD Device returns only one MCHE in a package, specifically
\_SB.PCI0.MCHC. Check kernel boot messages for absence of errors like
AE_NOT_FOUND related to named reference package elements such as
\_SB_.PCI0.RP04.MCHC.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I0a38cfc9bd38393cbf44f0e560c9525526d6bbf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89374
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The commit addresses an issue with discrete WIFI driver configuration
under root port 4 in the Google Fatcat mainboard. The problem involved
incorrect probe settings that allowed the WIFI driver device to remain
enabled even when its upstream device was disabled. This led to orphan
devices being misidentified as root devices within the Intel Power
Engine (PEP) structure, which in turn caused unnecessary MCHC devices
to be added under the root port.
The fix involves ensuring that the probe settings for the devices
managed by the driver are consistent with their upstream device
settings. Additionally, the RTD3 driver device type is now set to
generic, ensuring that only one PCI device exists under the root port.
This prevents the binding of device operations (ops) for the RTD3 driver
from interfering with the WIFI generic driver during the scan process.
The commit also resolves warnings related to leftover static devices and
prompts to check the devicetree.cb. The fix ensures that the probe
settings for WIFI_PCIE_6 and WIFI_PCIE_7 are properly configured,
preventing device misidentification and ensuring correct functionality.
BUG=none
TEST=Boot to OS and verify the DSDT tables. Ensure the _DSM function of
the PEPD Device returns only one MCHE in a package, specifically
\_SB.PCI0.MCHC. Check kernel boot messages for absence of errors like
AE_NOT_FOUND related to named reference package elements such as
\_SB_.PCI0.RP04.MCHC.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I40be48c056355d9e2a38b604849eb16565b8699d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89373
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use 0 instead of NULL when testing or initializing uintptr_t
fields, since NULL is only defined for pointers.
"data.3.lzma.bin" file is regenerated using:
util/cbfs-compression-tool compress file.bin /tmp/file.lzma.bin lzma
dd if=/tmp/file.lzma.bin of=file.lzma.bin skip=8 ibs=1
Change-Id: Ia1e7cc5052e842c7ef97ec7cec34919bbe1e2228
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
When commit 50a59d4464 ("device: Add Kconfig to prepare for reworked
verb table implementation") was created this mainboard was not in the
main branch and therefore was not accounted for. However, since it got
merged right before the commit mentioned above was merged, there was no
time to add it.
Add this Kconfig to fix the build system from failing.
Change-Id: If7382125122b4d54332f52d922d8af84ba51763c
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89368
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
*information* does not have plural, so use *This* instead of *These*.
Change-Id: I966373371cac4edd681f3b503e5f3a637fc28913
Fixes: a45c8441af ("lib: Add boot mode information to coreboot tables")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89227
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Seems to be the same board but with a Twin Lake processor.
VBT extracted from vendor firmware. This makes HDMI and
DisplayPort work.
Change-Id: I1018042802cbb8010888847226a2117fd9dfaeb0
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89281
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No modifications/assumptions about the codecs were made on these boards.
The Kconfigs were reverted using the following command:
find src/mainboard/purism -name 'Kconfig' | xargs git checkout main
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see CB:88656.
TEST= All boards passed regression test (CB:88763)
Change-Id: I2ee7a93392a57e8194cc8116c3fc55116336234f
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88686
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some boards did not provide the chip name for the audio codecs in the
comments, and therefore we made the following assumptions based off the
vendor ID:
fatal1ty_z87_professional:
- 0x11020011 -> Creative CA0132[3]
It should be noted that some factors (e.g. revision) can cause the chip
name to differ even with the same vendor ID. This is especially common
for Realtek audio codecs.
The following chip names were identified using external sources:
b75m-itx:
- 0x10ec0892 -> Realtek ALC892[1][5]
b75pro3-m:
- 0x10ec0892 -> Realtek ALC892[2]
z87_extreme3:
- 0x10ec0892 -> Realtek ALC892[1][6]
z87_extreme4:
- 0x10ec0900 -> Realtek ALC1150[4][7]
z87_pro4:
- 0x10ec0892 -> Realtek ALC892[1][8]
z87e-itx:
- 0x10ec0900 -> Realtek ALC1150[4][9]
z87m_extreme4:
- 0x10ec0900 -> Realtek ALC1150[4][10]
z87m_oc_formula:
- 0x10ec0900 -> Realtek ALC1150[4][11]
The Kconfigs were reverted using the following command:
find src/mainboard/asrock -name 'Kconfig' | xargs git checkout main
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see CB:88656.
References:
[1] Linux kernel: sound/hda/codecs/realtek/alc662.c:1101
[2] coreboot board status: kernel_log.txt
[3] Linux kernel: sound/hda/codecs/ca0132.c:10144
[4] Linux kernel: sound/hda/codecs/realtek/alc882.c:844
[5] https://www.asrock.com/mb/Intel/B75M-ITX/index.asp
[6] https://www.asrock.com/mb/intel/Z87%20Extreme3/
[7] https://www.asrock.com/mb/intel/Z87%20Extreme4/
[8] https://www.asrock.com/mb/Intel/Z87%20Pro4/
[9] https://www.asrock.com/mb/Intel/Z87E-ITX/
[10] https://www.asrock.com/mb/Intel/Z87M%20Extreme4/index.asp
[11] https://www.asrock.com/mb/intel/z87m%20oc%20formula/
TEST= All boards passed regression test (CB:88763)
Change-Id: I60ba4e8e048dfbf8ca5969251fd448ce3644d9e0
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
