mb/siemens/mc_rpl1: Send POST codes to NC FPGA via PCI

This board uses PCI to send POST codes to the NC FPGA. Enable the
feature of sending the POST codes to the NC FPGA via PCI so that the
POST codes are visible in coreboot.

TEST=Built and booted on mc_rpl1. Check that the POST Codes are
correctly displayed on the 7-segment display.

Change-Id: I95a1ac7121560b812aea36485c37f39e13de535a
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>

src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Kconfig

@@ -10,9 +10,25 @@ config BOARD_SPECIFIC_OPTIONS
 	select TPM_MEASURED_BOOT
 	select TPM_MEASURED_BOOT_INIT_BOOTBLOCK
 	select DRIVER_INTEL_I210
+	select NC_FPGA_POST_CODE
 
 config UART_FOR_CONSOLE
 	int
 	default 2
 
+config EARLY_PCI_BRIDGE_DEVICE
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0x1c
+
+config EARLY_PCI_BRIDGE_FUNCTION
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0x0
+
+config EARLY_PCI_MMIO_BASE
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0xfe400000
+
 endif # BOARD_SIEMENS_MC_RPL1

src/mainboard/siemens/mc_rpl/variants/mc_rpl1/Makefile.mk

@@ -3,3 +3,5 @@
 bootblock-y += early_gpio.c
 ramstage-y += gpio.c
 romstage-y += variant.c
+
+all-$(CONFIG_NC_FPGA_POST_CODE) += post.c

src/mainboard/siemens/mc_rpl/variants/mc_rpl1/post.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <nc_fpga.h>
+#include <types.h>
+
+void mainboard_post(uint8_t value)
+{
+	nc_fpga_post(value);
+}