SATA_DEVSLP1B and PEDET were simply missed, so configure them
Change-Id: Iface1f19c5a93f5a911861fbad7fa4b3f808bfef
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89577
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, it just puts them into a the same
format as the other Star Labs boards.
Change-Id: I849d0b50490eec6b6c58bd0fd29f57e434ba95c4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89575
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When Thunderbolt was disabled in the option table, only
VtdBaseAddress[3] was zero'd, when it should be
VtdBaseAddress[4] as well.
Change-Id: I63e3cefcb74c2ef31b5b0180d13a4720a6d7d0c2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89553
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, as the settings remain the same, and
it's only done as a pre-caution as FSP has been funny with VBT versions
before.
Change-Id: Ie7978e76286b3e2ff21fd0a28bfe51bdfd32f381
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89547
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add BT _PRR related methods to mitigate BT lost issue.
Refer to Intel TA#837249, toggling BTEN, BT_IF_SELECT, and
BT_RESET_GPIO to recovery BT device when BT became a low-speed usb
device.
BUG=b:451095940
TEST=Run reboot stress and check kernel log, BT could be recovery.
usb 3-10: new full-speed USB device number 4 using xhci_hcd
usb 3-10: New USB device found, idVendor=8087, idProduct=0033,
bcdDevice= 0.00
usb 3-10: New USB device strings: Mfr=0, Product=0, SerialNumber=0
usb 3-10: using ACPI '\_SB.PCI0.XHCI.RHUB.HS10' for 'reset' GPIO lookup
usb 3-10: USB disconnect, device number 4
usb 3-10: new low-speed USB device number 5 using xhci_hcd
usb 3-10: device descriptor read/64, error -71
usb 3-10: device descriptor read/64, error -71
usb 3-10: new low-speed USB device number 6 using xhci_hcd
usb 3-10: device descriptor read/64, error -71
usb 3-10: device descriptor read/64, error -71
usb 3-10: new full-speed USB device number 7 using xhci_hcd
usb 3-10: New USB device found, idVendor=8087, idProduct=0033,
bcdDevice= 0.00
Change-Id: I0d485a9102676624da28d5d681ea4510444e17bd
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89384
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
ReportingPchPmDisableEnergyReport has been 0 by default in all
FSP versions up until Meteor Lake. Set this to unify the
configuration between boards.
No applicable tests.
Change-Id: If9cdbb466bf8e4efc7a1577b0a1fec6270550d05
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89527
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These do not need to be configured, as they're configured
automatically on reset.
Change-Id: I26c9a42fa44b55208583859895f9a39016e76eac
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89523
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When configuring the touch_thc_i2c controlled touchpad and touchscreen
for the first time, referring to the fatcat code. The touchpad and
touchscreen could not be successfully bringup, since the touchpad and
touchscreen configured in the code are opposite to those in the fatcat
schematic diagram. According to the circuit schematic
NB7835CAA_SCH_MB_V1_A.pdf, modify the GPIO configuration and devicetree.
1. Configure GPIO as THC-I2C function.
2. Modify devicetree
touchpad ==> THC0
touchpanel ==> THC1
BUG=b:448030832 b:445817408
TEST=emerge-fatcat coerboot chromeos-bootimage
flash to DUT, touchpad and touchpanel can be found by `getevent`
Change-Id: I6826145f58d437e03683a4459ded3b7657cf616a
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89383
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the PinMux is configured correctly, these no longer
need to be set, as they're configured automatically on reset.
Change-Id: I03c6431f6ce7118444ef3672de32c5afa2e36441
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This doesn't do anything, so remove it.
Change-Id: Ic753d0f08bdc0e9dd839357eb73c9771d94e5c83
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Configure Pin Mix for Cs, Clk, Miso and Mosi to get the eSPI
GPIOs working as they should be.
Change-Id: I798f1e98f611a53e9c87f15e1e0f1679b9933bee
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89520
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The common settings are:
* Reorder Child Device mappings to prioritise EFP displays.
* Disable EFPx that are not present.
* eDP panel colour depth is 24-bit (8 bpc).
* POST brightness of 100.
* Minimum brightness of 0.
* DPST level of 2.
* PSR Enabled.
* DDRS Enabled.
Test=Boot all boards, check brightness levels are consistant, the
kernel recognises that PSR and DDRS are enabled, check all outputs
work.
Change-Id: I7eb6a110d25d4bcfd26ffdddd9ec666fc90a04b0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89515
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The macro USB2_PORTS_MID vs USB2_PORTS_TYPE_C essentially enables
or disables the PortResetMessage. This is only relevant to TCSS
ports.
Correct the macros accordingly.
Change-Id: I18a078c7f6fb937293e6159f05587b7e1f881512
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89513
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This isn't supported so remove it.
Change-Id: I8e8a87f1394199d3288ae27601069ad88e2fa74f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The IRQ97 will continue to be triggered, and cros_ec_irq_thread()
will be called all the time, even if GPP_E07 is high.
The following information will be continuously printed on the EC
console:
25-09-20 15:25:53.945[148.780609 HC 0x0067 err 9]
...
According to NB7835CAA_SCH_MB_V1_A.pdf,
change
PAD_CFG_GPI_SCI_LOW(GPP_E07, NONE, DEEP, LEVEL),
->
PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
can fix the interrupt exception.
BUG=b:445883867
TEST=emerge-fatcat coreboot and there is no HC error storm.
Change-Id: Ic151dce7881a6730a347eeae8f2e029fdc60bbd0
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89362
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the Elan touchpad configuration for moonstone AVL.
BUG=b:442964901
TEST=build firwmare and check the touchpad can work well in ALOS.
cat /sys/bus/i2c/devices/i2c-12/i2c-ELAN0000\:00/name
i2cdetect -y -r 12 -> 0x15 = UU
Change-Id: Ie105906fb54383dbf91513f81ab933653162ad4e
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89467
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the necessary configuration for the focaltech
touchscreen (FTSC1000) device, connected to I2C bus 38.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:442964901
TEST=emerge-fatcat coreboot and focaltech touchscreen can work well.
Change-Id: I7fb2f8b3c4ceb9d4bc7471d7eef23b0a18dca78a
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89465
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mainboard family is set based on the baseboard.
TEST=build/boot google/galtic, verify mainboard family set correctly
in SMBIOS.
Change-Id: Ifb5335c7dad43e8a75dd462a121d2eb711c51ccc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89453
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These boards all use PDM1 for the microphone topology, and so need to
override the baseboard default.
TEST=boot Win11 on omnigul, verify speakers/microphone work with
Coolstar's drivers.
Change-Id: I55a5886fc02a83640392854cd7132aa811dac6f3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89454
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change refactors `configure_backlight` function to accept a boolean
'enable' parameter. This provides more explicit control over the
backlight state.
BUG=b:319511268,b:319511268
TEST=emerge-rauru coreboot
Change-Id: Ia713dc792186a9a8080fd9d7ee02738fd372f531
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Options are organized to be as close to vendor firmware as possible.
Some options are not implemented for all variants. Those are either
excluded from build via preprocessor, or left visible but unused.
They will be squared off later.
TEST=abuild tested on the whole series.
TEST=Complete platform setup menu appears for mb/asus/p8z77-v_le_plus
with edk2/mrchromebox payload, with changes to front audio panel type
reflected in hardware.
Change-Id: I558012b28d098a90863e3ff6610017c2410c23ed
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This was supposed to be checked in the regression test script
(CB:88763), however it turns out Valgrind's Memcheck only works on the
heap memory and is unable to catch such errors.
The regression test script was modified to use AddressSanitizer which
can catch such errors, so this should not be a problem in subsequent
changes during the verb table rework.
To be safe, the previously merged commits were also checked with the new
regression test script:
f634121fa4 ("mb/purism: Replace verb tables with reworked implementation")
20d4042458 ("mb/asrock: Replace verb tables with reworked implementation")
2b7dbf80c9 ("mb/apple: Replace verb tables with reworked implementation")
970249694f ("mb/amd: Replace verb tables with reworked implementation")
94beaa7ab3 ("mb/acer: Replace verb tables with reworked implementation")
f3db3a19d5 ("mb/51nb: Replace verb tables with reworked implementation")
However, the following mini-HD code was checked manually, as figuring
out how to strip out minihd_init() was not worth the effort:
bc92d9a666 ("nb/intel/haswell/minihd.c: Add reworked verb table implementation")
69781b9806 ("soc/intel/broadwell/minihd.c: Add reworked verb table implementation")
Change-Id: Iea964fb8b92814b57d4c82412c47cf31fa48de66
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89376
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some boards did not provide the chip name for the audio codecs in the
comments, and were therefore identified using external sources:
h61m-a_usb3:
- 0x10ec0887 -> Realtek ALC887[1][5]
h61m-cs:
- 0x10ec0887 -> Realtek ALC887[1][6]
p8h61-m_pro:
- 0x10ec0887 -> Realtek ALC887-VD[3]
p8h67-i_deluxe:
- 0x10ec0892 -> Realtek ALC892[3][7]
p5gc-mx:
- 0x10ec0892 -> Realtek ALC662[2]
p5qc:
- 0x10ec0888 -> Realtek ALC1200[2]
p5ql-em:
- 0x10ec0888 -> Realtek ALC1200[8]
p8z77-m:
- 0x10ec0887 -> Realtek ALC887[1][9]
p8z77-v:
- 0x10ec0892 -> Realtek ALC892[3][10]
p8z77-v_le_plus:
- 0x10ec0889 -> Realtek ALC889[4][11]
The Kconfigs were reverted using the following command:
find src/mainboard/asus -name 'Kconfig' | xargs git checkout main
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see commit 31fc5b06a6
("device: Introduce reworked azalia verb table").
References:
[1] Linux kernel: sound/hda/codecs/realtek/alc882.c:839
[2] coreboot board status: kernel_log.txt
[3] Linux kernel: sound/hda/codecs/realtek/alc662.c:1101
[4] Linux kernel: sound/hda/codecs/realtek/alc882.c:842
[5] H61M-A/USB3 User's Manual (English), Version E8184
[6] H61M-CS User's Manual (English), Version E9069
[7] P8H67-I Deluxe User's Manual (English), Version E6964
[8] P5QL-EM user’s manual(English), Version E4165
[9] P8Z77-M User's Manual (English), Version E7075
[10] P8Z77-V User's Manual (English), Version E7074
[11] P8Z77-V LE PLUS User's Manual (English), Version E8001
TEST= All boards passed regression test (CB:88763)
Change-Id: Id2d4895bb40885f83d602b3a80805a84e348771b
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
This board uses PCI to send POST codes to the NC FPGA. Enable the
feature of sending the POST codes to the NC FPGA via PCI so that the
POST codes are visible in coreboot.
TEST=Built and booted on mc_rpl1. Check that the POST Codes are
correctly displayed on the 7-segment display.
Change-Id: I95a1ac7121560b812aea36485c37f39e13de535a
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
All mc_rpl boards have, like the mc_apl and mc_ehl variants, legacy
PCI devices which take longer to boot. To ensure their correct
enumeration, a delay is added before the PCI scan starts. The delay
value is provided by hwinfo.
TEST=Built and booted on mc_rpl board. Verified legacy PCI devices
enumerate correctly after delay implementation. Log excerpt while
testing function:
```
[INFO ] tlcl2_extend: response is 0x0
[DEBUG] TPM: Digest of `CBFS: hwinfo.hex` to PCR 3 measured
[NOTE ] Wait remaining 6595702 of 10000000 us for legacy devices...done!
[DEBUG] BS: BS_DEV_ENUMERATE entry times (exec / console): 6597 / 64 ms
[INFO ] Enumerating buses...
```
Change-Id: I97885a7cf060bc69c7fef75a9fa917bc8a176582
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89393
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Macros are generated using the hda-decoder utility.
TEST: update coreboot in ROM with this patch -> boot Ubuntu 24.04 again
-> the hda-decoder output before and after the update are the same
and the audio works.
Change-Id: I33d693a483c43a31d6dbb75a97b3ca5f5149fd69
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89371
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Configure GPP_F10, GPP_F11, GPP_F12, GPP_F13, GPP_F16, and GPP_F17
as no-connects by default. These GPIOs will be enabled in
fw_config.c if they are needed.
BUG=b:447648103
TEST='emerge-ocelot coreboot chromeos-bootimage`, flash and boot ocelot
and verify the AUDIO_ALC721_SNDW still works.
Change-Id: I7c07581e2b29bfc3e83314a065fba7d418e07c2a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
The DPTF parameters were defined by the thermal team.
Based on thermal table in b:448253910 comment#1
BUG=b:448253910
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I91ad12bdb58432b3c2b867278ec5b396553ac2b9
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89380
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add enums for the output pin widget node IDs for Realtek ALC887 [1] and
use these enums in the motherboard configuration.
[1] Figure 1, Block Diagram, ALC887-GR Datasheet, Rev. 1.0, 24 July 2008
Change-Id: Iaa2ebd7447a19dfc98b006c851f1605851c1ea5d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Because we use dummy ish in pujjoquince, so disable ish related gpio
when fw_config TABLET_MODE=TABLET_MODE_DISABLE
BUG=b:432649211
TEST=Build and boot to OS, check pujjoquince ish related gpio are closed.
Change-Id: Iab43f6d4ce3a6d31358ac0b902535ee3f5dad1e3
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
In 76e0f64035, it overrides
GPIO_PCH_WP in variant/gpio.h, however gpio.c includes
baseboard/gpio.h instead of variant/gpio.h. The wrong GPIO header
causes the test firmware.WriteProtectCrossystem to fail with the
wrong GPIO_PCH_WP pin number. Corrects the header file included in
gpio.c to fix the issue.
BUG=b:448313028
TEST=Pass firmware.WriteProtectCrossystem
Change-Id: I94b2384d03f8ce83f662a2b9dba4039f3d551b07
Signed-off-by: Derek Huang <derekhuang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89389
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 1e7908fa9f ("mb/google/skywalker: Set up all output GPIOs") set
up all output GPIOs to the desired initial value. However, as the
GPIO_USB3_HUB_RST_L pin is already pulled high in usb3_hub_reset() right
before the setup_chromeos_gpios() call, we should not pull it low again.
Otherwise all the USB3 hubs would stop working.
Fix the issue by moving the configuration from usb3_hub_reset() to
setup_chromeos_gpios(), where GPIO_USB3_HUB_RST_L is pull high to reset
USB3 hub.
BUG=none
TEST=emerge-skywalker coreboot
TEST=USB3 hub working properly during bootup
BRANCH=skywalker
Change-Id: Id53ddb033166f7fdcf6b5fc50b538ee29d5d85bb
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89388
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure PWR_EN and RST GPIO of fingerprint sensor.
BUG=b:438785495
TEST='emerge-fatcat coreboot' and boot into os,
fingerprint function is ok.
Change-Id: If896fa5c0600c4bef9ea2c67a30205bcf2689bd1
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89305
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The commit addresses an issue with discrete WIFI driver configuration
under root port 4 in the Intel PtlRvp mainboard. The problem involved
incorrect probe settings that allowed the WIFI driver device to remain
enabled even when its upstream device was disabled. This led to orphan
devices being misidentified as root devices within the Intel Power
Engine (PEP) structure, which in turn caused unnecessary MCHC devices
to be added under the root port.
The fix involves ensuring that the probe settings for the devices
managed by the driver are consistent with their upstream device
settings. Additionally, the RTD3 driver device type is now set to
generic, ensuring that only one PCI device exists under the root port.
This prevents the binding of device operations (ops) for the RTD3 driver
from interfering with the WIFI generic driver during the scan process.
The commit also resolves warnings related to leftover static devices and
prompts to check the devicetree.cb. The fix ensures that the probe
settings for WIFI_PCIE_6 and WIFI_PCIE_7 are properly configured,
preventing device misidentification and ensuring correct functionality.
BUG=none
TEST=Boot to OS and verify the DSDT tables. Ensure the _DSM function of
the PEPD Device returns only one MCHE in a package, specifically
\_SB.PCI0.MCHC. Check kernel boot messages for absence of errors like
AE_NOT_FOUND related to named reference package elements such as
\_SB_.PCI0.RP04.MCHC.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I0a38cfc9bd38393cbf44f0e560c9525526d6bbf2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89374
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The commit addresses an issue with discrete WIFI driver configuration
under root port 4 in the Google Fatcat mainboard. The problem involved
incorrect probe settings that allowed the WIFI driver device to remain
enabled even when its upstream device was disabled. This led to orphan
devices being misidentified as root devices within the Intel Power
Engine (PEP) structure, which in turn caused unnecessary MCHC devices
to be added under the root port.
The fix involves ensuring that the probe settings for the devices
managed by the driver are consistent with their upstream device
settings. Additionally, the RTD3 driver device type is now set to
generic, ensuring that only one PCI device exists under the root port.
This prevents the binding of device operations (ops) for the RTD3 driver
from interfering with the WIFI generic driver during the scan process.
The commit also resolves warnings related to leftover static devices and
prompts to check the devicetree.cb. The fix ensures that the probe
settings for WIFI_PCIE_6 and WIFI_PCIE_7 are properly configured,
preventing device misidentification and ensuring correct functionality.
BUG=none
TEST=Boot to OS and verify the DSDT tables. Ensure the _DSM function of
the PEPD Device returns only one MCHE in a package, specifically
\_SB.PCI0.MCHC. Check kernel boot messages for absence of errors like
AE_NOT_FOUND related to named reference package elements such as
\_SB_.PCI0.RP04.MCHC.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I40be48c056355d9e2a38b604849eb16565b8699d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89373
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
