mb/google/fatcat/var/lapis: Update gpio GPP_E07 configuration

The IRQ97 will continue to be triggered, and cros_ec_irq_thread()
will be called all the time, even if GPP_E07 is high.
The following information will be continuously printed on the EC
console:
25-09-20 15:25:53.945[148.780609 HC 0x0067 err 9]
...

According to NB7835CAA_SCH_MB_V1_A.pdf,
change
PAD_CFG_GPI_SCI_LOW(GPP_E07, NONE, DEEP, LEVEL),
->
PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
can fix the interrupt exception.

BUG=b:445883867
TEST=emerge-fatcat coreboot and there is no HC error storm.

Change-Id: Ic151dce7881a6730a347eeae8f2e029fdc60bbd0
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89362
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/fatcat/variants/lapis/gpio.c

@@ -211,7 +211,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_E06:     Not used */
 	PAD_NC(GPP_E06, NONE),
 	/* GPP_E07:     EC_SOC_INT_ODL */
-	PAD_CFG_GPI_SCI_LOW(GPP_E07, NONE, DEEP, LEVEL),
+	PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
 	/* GPP_E08:     Not used */
 	PAD_NC(GPP_E08, NONE),
 	/* GPP_E09:     USBA0_OC_ODL ==> USB_OC0# */