The darp10 has a second fan but no dGPU. The NFAN Method must exist, so
use the default hwmon names of "fan1" and "fan2" for labels.
Change-Id: I553deefea374b9dd916be6611850fca61afd490d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Fixes using USB3 devices at USB3 speeds in all ports.
This fix requires `EnableTcssCovTypeA`, which is not available in the
coreboot FSP headers and not available upstream as Intel will not make a
Client FSP release.
Change-Id: I9bc6c5fc4c13bfa2e31ee1ce334b91e151373b6e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Let coreboot configure the eSPI GPIOs, to ensure they are correct
rather than letting FSP do it.
Change-Id: I14dc740be9a770b662dd61bfdc4f4ace8973d998
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
1. frequency changes to 366 kHz from 457 kHz
2. tHIGH changes to 0.8 us from 0.514 us
3. tSU:STA changes to 0.68 us from 0.56 us
BUG=b:417375114
BRANCH=firmware-rex-15709.B
TEST=1.emerge-rex coreboot chromeos-bootimage
2.EA is measured and verified by HW
Change-Id: I996885a9acf2eea7f49ecf2fcd4f7d3fda842c8e
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
According to the HW schematics, GPP_A14 should be set as USB_OC1
for the A0 port, but it was found that the USB3_A0 port did not
match the configuration, so this has been corrected.
BUG=b:410481989
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I2fcf15ca008eca6c74f4020c3fa7af8863a56a00
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87637
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Perform early initialization of essential ChromeOS-specific
peripherals and GPIOs within the `bootblock_mainboard_init()`
function. This ensures critical communication paths and
hardware states are configured early in the boot process.
Specifically, this commit:
- Calls `setup_chromeos_gpios()` to configure general AP/EC
interrupts, and conditionally sets up GPIOs for the FPMCU
(reset, boot mode, power rails) and Soundwire amplifiers
(enable pins).
- Initializes the I2C bus for the H1/TPM via `i2c_init()`
when `CONFIG_I2C_TPM` is enabled.
- Initializes the SPI bus for the ChromeEC via `qup_spi_init()`
when `CONFIG_EC_GOOGLE_CHROMEEC` is enabled.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: Ic29de4c1f48f33bd1ce6a4385bfc22fdef7ab911
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87642
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Lemur Pro 13 (lemp13) is an Intel Meteor Lake-U based board.
There are 2 variants to differentiate which keyboard design the unit
uses, as they require different EC firmware.
Change-Id: Icac8c7dafd6371881622d797f399f8ddbe13cbce
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Since commit bb66d07d41
"soc/amd/common: Always use genoa SPI MMAP driver" the ROM size can be
actually be greater than 16MiB on all AMD platforms without seeing a
boot failure. Since still only 16MiB of the SPI flash are MMAPed,
the FMAP should not be extended, and if so should only contain non x86
firmwares in the upper 16MiB of flash.
Now that common code supports ROM_SIZE greater than 16MiB select the
correct BOARD_ROMSIZE_KB for each mainboard.
Change-Id: Icdce01bddbc4873ba42ceddcda6d9075f5a42914
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Perform comprehensive peripheral initialization across romstage
and ramstage for the Bluey mainboard. This brings up essential
ChromeOS components and manages their power/reset sequences.
Key changes include:
- FPMCU Power & Reset:
- Enable `GPIO_EN_FP_RAILS` in romstage for power rail
stabilization (conditional on SPI fingerprint).
- Deassert `GPIO_FP_RST_L` in ramstage once FPMCU power is stable.
- QUPv3/GPI Peripherals:
- Load GSI (Generic Software Interface) firmware for
QUP_0/1/2_GSI_BASE.
- Initialize various QUPv3 Serial Engines (SE) in ramstage:
- UART for console (if not `CONFIG_CONSOLE_SERIAL`).
- I2C for Touch and Trackpad controllers.
- UART for Bluetooth module.
- SPI for the Fingerprint module (conditional on Kconfig).
- Display Initialization: Add a placeholder function `display_startup()`
in ramstage.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: Iaa800e89eb521dc9d7b0a01984ca07b46a2a29d6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87643
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This option isn't hooked up to anything currently, so remove it.
Change-Id: I01cddc6dbffa5a0cf914ef3c529366ee6ceaaf02
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87560
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This option isn't hooked up to anything currently, so remove it.
Change-Id: I1777ee1910bb635181a348c55642aca1ff711b02
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Now that a global CFR object exists to set the console output level,
use it instead of duplicating the object for each mainboard.
TEST=build lite_adl_sb
Change-Id: Ie39e77e8345381a018e3df80aebe3126616fc556
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This commit configures the firmware splash logo's vertical alignment to
be centered (middle) for the Fatcat variants: Felino, Francka, and
Kinmen.
This is achieved by setting the 'logo_valignment' field to
'FW_SPLASH_VALIGNMENT_MIDDLE' within the 'common_soc_config' register.
BUG=b:409718202
TEST=Able to see FW splash screen at the middle of the screen while
booting google/fatcat.
Change-Id: Idf7f06cac89c14f58e5a3bcab5fe61d72171352b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
In preparation for adding additional Haswell based Dell Latitude
laptops, rework the E7240 port to use a variant scheme.
TEST=Timeless build with CONFIG_INCLUDE_CONFIG_FILE=n for the E7240 did
not change between main and this commit
Change-Id: I3031910db6d817824320320f137b0f99cdfe1d9a
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Enable support for managing system options via CFR, and select it by
default when using edk2 with SMMSTORE.
TEST=build/boot wyvern w/edk2 payload
Change-Id: I6ccf0c9c50babb3134669c977eb27b7b3f567546
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87566
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable support for managing system options via CFR, and select it by
default when using edk2 with SMMSTORE.
TEST=build/boot fizz w/edk2 payload
Change-Id: I211a91f16622b048d15ebe373106b0f70b429312
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enable support for managing system options via CFR, and select it by
default when using edk2 with SMMSTORE.
TEST=build/boot guado w/edk2 payload
Change-Id: I1d407a702513bcffde6b1578469b6e307e5db662
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enable support for managing system options via CFR, and select it by
default when using edk2 with SMMSTORE.
TEST=build/boot panther w/edk2 payload
Change-Id: Ic5dff1f046de2b477361822772dd1add64d608af
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Meliks' domain_vr_config[] parameters were from pirrha at the
beginning, remove this configuration overrides to use the default
configufation of SoC to avoid potential side effect from it.
BUG=b:409205469
TEST=Built and boot
The score gap of 3D mark and Geekbench was within 1 percent in
our internal test
Change-Id: I6a34b6a3c3694b4e7084a515b6f0d2aeaeadbd36
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Enable the GNA PCI device, and include the ACPI stub so the OS driver
can attach.
TEST=build/boot Win10 on google/brya (banshee)
Change-Id: Ib97278820d93a8fae52a74f36a5f60d9a9b2b363
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77577
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Not needed for this is board, and using the default timeout value
causes boot delays when the public IOT FSP is used.
TEST=build/boot starbook MTL.
Change-Id: Ia87e4239dbff57894af4c7b4b2857f809007843d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87569
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure these to match the other Star Labs boards.
Change-Id: Icb57f58902cc6cf2e1faf40194a6a500c6280882
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The existing 200ms `generic.reset_delay_ms` for the Francka variant
is unnecessarily long. This commit reduces the delay to 10ms.
A 10ms delay has been verified as adequate for the hardware to reset
correctly, maintaining touchscreen operation post-boot. This change
contributes to a slightly faster resume sequence (optimized by ~190ms)
by removing a superfluous wait time.
BUG=b:411164455
TEST=Able to boot google/francka with touchscreen functional.
Change-Id: I8984617669c804b7d4ad32b3c67d87f3027fa1c1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Due to the ISH UART configuration change and the need to support
different phases of the motherboard, we use the board ID to
distinguish which configuration to apply.
BUG=b:415605630, b:411249861
TEST=emerge-nissa coreboot
Change-Id: Id6e0e67595d3b4a44382ce82d160fe865cda275c
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
As per the requirement, the ISH UART needs to be the same as Trulo, so
swap ISH UART from UART1 to UART0. And configure ISH_UART0 GPIO;
if not used, the pins will be set to NC. Additionally, the LCD_CBL_DET#
pin has been changed from GPP_D14 to GPP_D18.
BUG=b:415605630, b:411249861
TEST=emerge-nissa coreboot
Change-Id: I88bca9a56fa96ad0a52c29fec12b8d4dbee23be4
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87535
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Make use of the alias names defined in the chipset devicetree. Remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: I79de952d95798aa3c241e7864223c63c0a72ce31
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83524
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add support for yet another of these LGA1155 boards. Nothing too fancy,
just another slightly different combination of the same chips.
Working:
- Booting to Arch Linux using SeaBIOS (current version)
- Native RAM init
- Realtek Ethernet NIC
- Some rear USB 2.0 and 3.0 (ASM1042) ports (did not test all)
- At least one SATA port (did not test all)
- libgfxinit to initialise a DVI-D display
- VBT (extracted from `/sys/kernel/debug/dri/0/i915_vbt`)
- PCIe x16 slot
- Both PCIe x1 slots
- EHCI debug (one of the rear USB 2.0 ports)
Not working:
- Automatic fan speed control (known limitation of Super I/O code)
Untested:
- HDMI, VGA
- Internal flashing (board was ported using an EM100Pro)
- Audio
- Front USB ports
- PS/2 ports
Change-Id: I18b116d265e0b7105e13a317b552aab0e4bbc762
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86726
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update VBT to one extracted from newer Lenovo UEFI, version FWKTBFA.
The newer VBT has build number 1037 and supports Kaby Lake graphics,
while the old VBT with build number 1000 only supports Skylake.
The old VBT starts with $VBT_SKYLAKE while the new one starts with
$VBT_KABYLAKE.
TEST=Insert CPU with integrated HD 630 graphics (i3-7100) and check if
all video outputs work in firmware.
Change-Id: I5e108d4ad8bf0663f3e1fa32145e40ea9babeac5
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
These three boards use <soc/intel/common/acpi/dptf/dptf.asl> and should skip generating the TCPU device via SSDT, so select
SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL to make that happen.
TEST=build/boot drallion, hatch, and sarien. Dump ACPI and verify no
duplicate TCPU ACPI device, verify no ACPI errors in dmesg.
Change-Id: I6070e5291ce2476fc1c24d39583fcca94bed1395
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit introduces the GPIO configuration support for the T4 LP5
Reference Validation Platform (RVP). It includes a table that outlines
the differences in GPIO configuration between the T3 LP5 RVP and T4 LP5
RVP. The GPIO differences are applied when the board ID is recognized as
T4.
BUG=none
TEST=Ensure the T4 RVP boots to the OS, then verify the GPIO pad
configurations by inspecting the output from /sys/kernel/debug/pinctrl.
Check that the GPIO PADs match the expected configuration for the T4
board.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ica870752bed2ba47c73d8fcd5f2f41b9cc6db65a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87447
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit introduces support for the T4 LP5 board memory
configuration within the ptlrvp mainboard. The addition includes
defining the specific memory configurations such as data and strobe
signal mappings, early command training, and memory part ID
assignments. By implementing these changes, compatibility and
functionality are ensured for systems using the T4 LP5 board.
The memory configuration is specified for LP5 type memory with
detailed DQ and DQS mapping for different DDR channels. This
facilitates accurate signal routing and memory initialization.
Additionally, updates to associated Makefiles and documentation files
reflect these new memory parts (Hynix H58G56BK8BX068) and their IDs,
ensuring proper recognition and usage during system builds.
BUG=none
TEST=Build and verify system initialization on the T4 LP5 board with
the updated memory configuration. Confirm that memory training and
setup proceed correctly with the newly supported memory part.
Change-Id: Ia6e862af8c322fe4467465557c416d4171796e83
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87422
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the mainboard directory for Intel's ptlrvp variant, ensure that the
`variant.c` file is compiled during the ramstage build process. This
adjustment enables the execution of variant_update_soc_chip_config()
for ptlrvp in ramstage, addressing CNVi Wi-Fi-related issues.
BUG=None
TEST=Verify that variant.c is compiled correctly in ramstage for
ptlrvp.
Change-Id: Iec9591aac536abfdd36dfba8a8fea689830ee41a
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87570
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
This commit overrides the `logo_valignment` setting in the
`common_soc_config` for the Fatcat board variant.
The vertical alignment for the firmware splash screen logo is now set to
`FW_SPLASH_VALIGNMENT_MIDDLE`, which places the top edge of the logo at
the vertical midpoint of the screen.
BUG=b:409718202
TEST=Built and booted google/fatcat.
Change-Id: I82cb0f9e06f23fb441011b9714284ac52a76d818
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Found that certain pins did not change according to the fw_config
settings. After tracing the code, discovered that
fw_config_gpio_padbased_override() was not being called, so this change
fixes the issue.
BUG=b:410481989
TEST=emerge-nissa coreboot
Change-Id: I07fb7860b32bae4922783fe437baafdd1c86482e
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87546
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Add/update FP enable/disable based on SKU ID. This is meant
to resolve a UMA issue with devices that had the FPMCU populated on
non-fp devices. Since the FPMCU is present, and the firmware enables
the power GPIO's based on variant, not SKU, the devices were reporting
data on fingerprint errantly. Specify the SKUs which should not have a
FP sensor and default to true to maintain the legacy behavior for
undefined devices and limit risk. Variants which do not have FP SKUs
will be unaffected.
BUG=b:354769653
TEST=Flash on device, test FP.
Disable test SKU, flash on device, test FP.
To test, run `ectool --name=cros_fp version` in the shell
When enabled, the fpmcu fw version should be displayed.
When disabled, an error should be displayed because the fpmcu
is inaccessible.
Change-Id: I9811721d0b345614e10ac27946ad45b6ec6f7494
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86826
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Delete the "TODO: Update for Phoenix" comment from files that have
already been updated in the previous chained patches (CB:85631,
CB:85632, CB:85633).
Change-Id: I137dbba5094ae8cbf842b45d6137c5b0528e5413
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85719
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.
Set these all to sample on RSMRST.
Change-Id: I557bfc1339bad169753640c9404813305a16024e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This patch removes device entries from the Ocelot mainboard
devicetree that do not exist in the Wildcat Lake SoC. This ensures
that the Ocelot firmware compiles without any errors when device
tree changes of Wildcat Lake SoC are added in the subsequent patches.
Key changes:
- Remove the following devices, which are not present in the
Wildcat Lake SoC, from Ocelot:
ipu
tbt_pcie_rp2
tbt_pcie_rp3
tcss_dma1
pcie_rp9
tcss USB port 2 & 3
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: Ib09f66f2e567f3f42810215bca8956c7cee7b646
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87479
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the `fill_lb_gpios` function in
`src/mainboard/google/bluey/chromeos.c` to include additional
GPIO states for Chrome OS diagnostics.
The following GPIOs are now reported:
- GPIO_SNDW_AMP_0_ENABLE: "Speaker 0 enable" (active high)
- GPIO_SNDW_AMP_1_ENABLE: "Speaker 1 enable" (active high)
- GPIO_SD_CD_L: "SD card detect" (active low), reported
conditionally if CONFIG_MAINBOARD_HAS_SD_CONTROLLER is enabled.
BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.
Change-Id: I0063e8190571241edda64165b9ade9c4331a3499
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit introduces several new GPIO definitions and a Kconfig
option for the Bluey mainboard to support additional hardware features.
Kconfig changes:
- MAINBOARD_HAS_SD_CONTROLLER: To indicate the presence of an SD card
controller. It defaults to 'n'.
GPIO changes (in board.h):
- Soundwire Amplifier GPIOs:
- GPIO_SNDW_AMP_0_ENABLE (GPIO 204)
- GPIO_SNDW_AMP_1_ENABLE (GPIO 205)
- Display specific GPIOs:
- GPIO_PANEL_POWER_ON (GPIO 70)
- GPIO_PANEL_HPD (GPIO 119)
- SD Card specific GPIO:
- GPIO_SD_CD_L (GPIO 71): This GPIO is conditionally defined based
on the new CONFIG_MAINBOARD_HAS_SD_CONTROLLER option.
Source: Bluey schematics (dated 04/15).
BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.
Change-Id: I556b06bff73805c6451a5f8cf291c83cd0431465
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
This commit introduces support for DDR5 memory configuration on the
PTL RVP DDR5 board. It adds the necessary board ID for PTLP_DDR5_RVP
and integrates a new DDR5 memory configuration within the variant
parameters. The memory configuration includes settings such as
resistor values, sagv values, early command training, and
DDR5-specific training parameters.
Additionally, SPD information retrieval is adapted to accommodate
DDR5-specific settings, such as DIMM module topology and SMBus
addresses.
BUG=none
TEST=Boot to OS with PTL RVP DDR5 board and verify memory
initialization.
Change-Id: I7e3bbb66edcbf4d4a10fcf6899156f125dc3d529
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87179
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Was inadvertently left out when this board was created.
TEST=build, verify ramstage.o created in variant subdir of build dir.
Change-Id: I3c728ba2abe94be4115a60d3a532cf0a19bec33c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add a CFR option to boot using the native panel resolution, rather than
a fixed/scaled video mode. This option selects between two VBT files:
one with the 'fixed mode' flag enabled, and one with it disabled.
This feature is mainly a workaround to a GNOME-related bug which
causes the creation of a 2nd display at the boot resolution. This
2nd display being a lower/different resolution than the native
panel resolution causes severe flickering/artifacting rendering
the display unusable unless this 2nd phantom display is disabled
on every boot.
Change-Id: I9e39258ce0171aab425150679d1ce30d69b2b1ef
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add a CFR option to boot using the native panel resolution, rather than
a fixed/scaled video mode. This option selects between two VBT files:
one with the 'fixed mode' flag enabled, and one with it disabled.
This feature is mainly a workaround to a GNOME-related bug which
causes the creation of a 2nd display at the boot resolution. This
2nd display being a lower/different resolution than the native
panel resolution causes severe flickering/artifacting rendering
the display unusable unless this 2nd phantom display is disabled
on every boot.
Change-Id: I275b5f8455fed58c0167e3a69db27bbc21577db0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87494
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
For boards for which set the 'Fixed Mode at boot' flag in the VBT, add
a CFR option to boot using the native panel resolution, rather than
a fixed/scaled video mode. This option selects between two VBT files:
one with the 'fixed mode' flag enabled, and one with it disabled.
This feature is mainly a workaround to a GNOME-related bug which
causes the creation of a 2nd display at the boot resolution. This
2nd display being a lower/different resolution than the native
panel resolution causes severe flickering/artifacting rendering
the display unusable unless this 2nd phantom display is disabled
on every boot
Change-Id: Ia75727f393744caf9062763e6118c1e2601512fa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
