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mb/trulo/var/uldrenite: Swap ISH UART from UART1 to UART0

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As per the requirement, the ISH UART needs to be the same as Trulo, so
swap ISH UART from UART1 to UART0. And configure ISH_UART0 GPIO;
if not used, the pins will be set to NC. Additionally, the LCD_CBL_DET#
pin has been changed from GPP_D14 to GPP_D18.

BUG=b:415605630, b:411249861
TEST=emerge-nissa coreboot

Change-Id: I88bca9a56fa96ad0a52c29fec12b8d4dbee23be4
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87535
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
This commit is contained in:
John Su 2025-05-05 15:21:32 +08:00 • committed by Matt DeVillier
commit 3fe4b00966
2 changed files with 12 additions and 8 deletions
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16
src/mainboard/google/brya/variants/uldrenite/gpio.c
View file

@ -143,18 +143,18 @@ static const struct pad_config gpio_table[] = {
PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG),
/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG),
/* D13 : UART0_ISH_RXD ==> NC */
PAD_NC(GPP_D13, NONE),
/* D14 : UART0_ISH_TXD ==> LCD_CBL_DET# */
PAD_CFG_GPO(GPP_D14, 1, DEEP),
/* D13 : UART0_ISH_RXD */
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
/* D14 : UART0_ISH_TXD */
PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
/* D15 : GPP_D15 ==> SOC_TS_I2C_RST# */
PAD_CFG_GPO_LOCK(GPP_D15, 1, LOCK_CONFIG),
/* D16 : ISH_UART0_CTS# ==> SOC_TS_I2C_INT# */
PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT),
/* D17 : NC ==> UART1_ISH_RX_DBG_TX */
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2),
/* D18 : NC ==> UART1_ISH_TX_DBG_RX */
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF2),
/* D17 : NC */
PAD_NC(GPP_D17, NONE),
/* D18 : LCD_CBL_DET# */
PAD_CFG_GPO(GPP_D18, 1, DEEP),
/* D19 : I2S_MCLK1_OUT ==> NC */
PAD_NC(GPP_D19, NONE),

4
src/mainboard/google/brya/variants/uldrenite/variant.c
View file

@ -50,6 +50,10 @@ static const struct pad_config ish_disable_pads[] = {
PAD_NC(GPP_B6, NONE),
/* D1 : ISH_GP1 ==> NC */
PAD_NC(GPP_D1, NONE),
/* D13 : UART0_ISH_RXD ==> NC */
PAD_NC(GPP_D13, NONE),
/* D14 : UART0_ISH_TXD ==> NC */
PAD_NC(GPP_D14, NONE),
/* E9 : SOC_ACC2_INT ==> NC */
PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
};