mb/google/{drallion,hatch,sarien}: Skip adding DTT/TCPU to SSDT

These three boards use <soc/intel/common/acpi/dptf/dptf.asl> and should skip generating the TCPU device via SSDT, so select
SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL to make that happen.

TEST=build/boot drallion, hatch, and sarien. Dump ACPI and verify no
duplicate TCPU ACPI device, verify no ACPI errors in dmesg.

Change-Id: I6070e5291ce2476fc1c24d39583fcca94bed1395
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/mainboard/google/drallion/Kconfig

@@ -22,6 +22,7 @@ config BOARD_GOOGLE_BASEBOARD_DRALLION
 	select MAINBOARD_USES_IFD_EC_REGION
 	select SMBIOS_SERIAL_FROM_VPD if VPD
 	select SOC_INTEL_COMETLAKE_1
+	select SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE
 	select SYSTEM_TYPE_LAPTOP

src/mainboard/google/hatch/Kconfig

@@ -26,6 +26,7 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
 	select MAINBOARD_HAS_TPM2
 	select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE
 	select SOC_INTEL_COMETLAKE_1
+	select SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL
 	select SPI_TPM
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_GOOGLE_CR50

src/mainboard/google/sarien/Kconfig

@@ -20,6 +20,7 @@ config BOARD_GOOGLE_BASEBOARD_SARIEN
 	select MAINBOARD_HAS_TPM2
 	select MAINBOARD_USES_IFD_EC_REGION
 	select SMBIOS_SERIAL_FROM_VPD if VPD
+	select SOC_INTEL_COMMON_BLOCK_DTT_STATIC_ASL
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SOC_INTEL_COMMON_BLOCK_SMM_ESPI_DISABLE
 	select SOC_INTEL_WHISKEYLAKE