The SoC won't be able to boot without dram.elf. Therefore, we should
always expect the file to exist in build time.
BUG=none
TEST=emerge-rauru coreboot
BRANCH=none
Change-Id: Ib902dc4778f34a144dddf847c283fe77d4c776f6
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85441
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The parentheses are missing in the mtk_scp macro definition.
The only usage is
SET32_BITFIELDS(&mtk_scp->scp_clk_on_ctrl,
SCP_CLK_ON_CTRL, 1);
I guess that bit is already set by default, so there's no ULPOSC clock
issue found so far.
BUG=none
TEST=none
BRANCH=cherry
Change-Id: I2dbb5c465ee60f0c4dce8ff77b8d3a39db42e4f5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
HW TX tracking works by writing a pattern to the designated DRAM buffer
and then reading it back automatically to calculate the appropriate TX
time delay. To avoid writing the pattern to system-used memory, we need
to permanently reserve last 64KB memory on each rank for the HW TX
tracking feature.
BUG=b:317009620
TEST=Reserve memory ok
Firmware shows the following log with 12GB DDR board:
00000001ffff0000-00000001ffffffff: RESERVED
000000037fff0000-000000037fffffff: RESERVED
Change-Id: I042a74c7fbdc0d3dc19dd6bfd2bf021fe1c2b5fc
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85124
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
It is unnecessary to look up PMIF controller by mstid in multiple
functions. Just pass `arb` to these functions in order to avoid
redundant calls to get_pmif_controller().
BUG=none
TEST=compiled
Change-Id: I907d6ff029827e4afe4f1d05e39c8dd662c7c45e
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85327
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enum is useful for improving readability because of the meaningful enum
names. Names such as "FREQ_260MHZ = 260", however, don't provide any
extra information of the value itself. Therefore, rename those enums to
PMIF_TARGET_FREQ_MHZ to better reflect its usage.
Change-Id: I420b909a76973a040b96feb2bcb93d3640b086b5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85204
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename the arguments of pmif_ulposc_check() and pmif_ulposc_cali()
to make the frequency unit clearer.
Change-Id: I7719fd4dc43edd47bf014af13fb57ad38f43778c
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
MT8196 equips new DPM hardware which is different from precedent SoCs.
Therefore, we need implement a new DPM loader (said version 2) to run
the blob. Considering the version iteration, rename the original dpm to
dpm_v1.
TEST=Build pass.
BUG=b:317009620
Change-Id: I07afb8f5c23e96aad3c6cb0887cb7efd16ebf296
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Add version two of the DPM driver for DVFS and DRAM low power feature.
MT8196 equips new DPM hardware which is different from precedent SoCs.
Therefore, we implement a new DPM loader (said version 2) to run the
blob. The new DPM driver includes following features.
- Simplify the DPM loading flow without the needs of waking DPM SRAM up
and initializing bootargs.
- Use the broadcast function to ensure that the DPM load and reset
operations performed on channel A will be synchronized to the other
three channels.
TEST=Full calibration pass.
BUG=b:317009620
Change-Id: I77e1ac252b00ab9c4864cc308f20da4a79714e4c
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85121
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Remove <assert.h> when it is not used.
Change-Id: Icb8ee7dcfd05e0a3131d02d1bc8fe150bbf9527b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85164
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Lastbus is a bus debug tool. When the bus hangs, the bus transmission
information before resetting will be recorded.
The watchdog cannot clear it and it will be printed out on the serial
console for bus hanging analysis.
TEST=build pass, and check log with:
[INFO ] ******************* MT8196 lastbus ******************
[INFO ] --- debug_ctrl_ao_APINFRA_IO_AO 0x10155000 37 ---
[INFO ] 00402504
[INFO ] c34b00d6
[INFO ] 61804050
[INFO ] 00051840
[INFO ] 10401610
BUG=b:317009620
Signed-off-by: Xiwen Shao <xiwen.shao@mediatek.corp-partner.google.com>
Change-Id: Ib030d88faa2d4d6f6a8501f8c752deeafff92c5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Add support for MT8196 DRAM calibration. DRAM parameters and related
constants are added in dramc_param.h and dramc_soc.h. As MT8196's
dramc_param struct size is different from other MediaTek SoCs,
replace the hardcoded RW_MRC_CACHE size in common code with a constant
derived from chromeos.fmd.
The common emi.c can be reused for MT8196 as well, so remove the
duplicate mt8196/emi.{c,h}.
Enable MEDIATEK_DRAM_BLOB_FAST_INIT to allow running DRAM fast
calibration via the DRAM blob.
Test=Build pass
BUG=b:317009620
Change-Id: Ifeaf73e31b29ef376a28ca2721dba0d4866d6e8b
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85098
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the checkpatch error:
Macros with complex values should be enclosed in parentheses
Change-Id: Ia0e4582c1dd19ed3f757a2cb3c3fc33138302d74
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85001
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Map a proper DRAM range for memory test during calibration.
TEST=memory test passed on Rauru
BUG=b:317009620
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Change-Id: I06f31ef14715897ba889076d78b8c2d015dd08ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85035
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SPI controller driver code with support for 8 buses (SPI0 to SPI7).
Test=Build pass, verify the wavefroms for SPI0~7 are correct.
BUG=b:317009620
Change-Id: I10dd1105931c4911ce5257803073b7af76115c75
Signed-off-by: Liya Li <ot_liya.li@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84930
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PLL and clock init code, frequency meter and APIs for raising
little CPU frequency and set tvdpll frequency.
TEST=build pass and driver init ok
BUG=b:317009620
Signed-off-by: Guangjie Song <guangjie.song@mediatek.corp-partner.google.com>
Change-Id: Icac99fb210c87c8b7b14af627fbd2f14e4c47240
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Rather than using a static array size for the `offset` variable, use a
pointer named `offsets` that points to a dynamically allocated array. A
separate variable called `offset_size` stores the size of this array.
TEST=emerge-corsola coreboot && emerge-geralt coreboot
Change-Id: I4b89c27fd693ee08e670c1a9ab4cbdbec220bee7
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Irq2axi translates wire-based interrupt into message signal interrupt.
Since MT8196 uses legacy wire-based interrupt, this feature needs to be
disabled. If the interrupt is not handled, it will cause the system fail
to boot.
TEST=Build pass, check irq2axi_disable log and the interrupt can be
correctly handled by checking /proc/interrupts.
BUG=b:317009620
Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84896
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
De-assert PERST# at romstage to reduce the waiting time in ramstage.
BUG=b:361728592
TEST=The boot time improves 62ms
Change-Id: I2cd5cd59e7513b6e4036c3e8013a3c7322d2f787
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
The size of the inner array of the 2-dimensional array pad_funcs should
be 4 instead of SPI_BUS_NUMBER (6). This bug leads to two extra
gpio_set_mode() calls with unexpected GPIOs.
Inspecting spi.o, the data immediately after the .rodata.pad_funcs
section is .rodata.spi_ctrlr_bus_map, with the following data:
00000428 00 00 00 00 00 00 00 00 00 00 00 00 05 00 00 00
00000438 00 00 00 00 00 00 00 00 ...
This is equivalent to the following calls:
gpio_set_mode(GPIO(GPIO05), 0);
gpio_set_mode(GPIO(GPIO00), 0);
The second call is already included in the pad_funcs array, so the first
call is the only practical impact of this bug.
Change-Id: I9c44f09b3cdadbbf039b95efca7144f213672092
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add PCIe driver for MT8196 platform.
According to the PCIe CEM specification, the deassertion of PERST#
should occur at least 100ms after the assertion. To ensure the 100ms
delay requirement is met and to save delay time in the ramstage, add
an early init data region to store the elapsed time since assertion.
This will speed up the boot time by 100ms.
PCIe port 1 and port 2 share the same PCIe resources, but PCIe port 2 is
not used. Therefore, in mtk_pcie_pre_init(), make sure PCIe port 2 is
reset to prevent interference with PCIe port 1.
TEST=Build pass, show pcie init pass log:
mtk_pcie_domain_enable: PCIe link up success (1)
BUG=b:317009620
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I826a96822e88972bcd4966b6681797a646adf3d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
The newly added enums and struct members will be used by MT8196.
BUG=none
TEST=emerge-corsola coreboot; emerge-geralt coreboot
Change-Id: I32e758cc4244114073606c418a69e0467cdf1039
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84773
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8196 has different pmif_spmi_arb and pmif_spi_arb configurations. Move
the common pmif data to a separate file in order to reuse common/pmif.c
as much as possible.
BUG=none
TEST=emerge-corsola coreboot; emerge-geralt coreboot
Change-Id: I24643ce58a57b9cc3c5220bc06a85b141b366eee
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
MT8196 has differenet configurations from other platforms. Make
CAL_TOL_RATE and CAL_MAX_VAL as per SoC configuration in order to reuse
common/pmif_clk.c
BUG=none
TEST=emerge-corsola coreboot; emerge-geralt coreboot
Change-Id: Iefc8180e1719d9796df7457b619a8792ceb762b2
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84771
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This fixes the following warning with clang (18.1.6):
src/soc/mediatek/mt8196/gpio_eint.c:259:44: error: '_Static_assert' with no message is a C23 extension [-Werror,-Wc23-extensions]
259 | _Static_assert(ARRAY_SIZE(eint_data) == 293);
| ^
|
Change-Id: I934b6d7ee8e8a0c204a4e328331c3ff3cd0f07de
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84618
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After reboot, the system does not need to serve pending IRQ from
systimer. Therefore, clear systimer IRQ pending bits in init_timer().
For that to work, the systimer compensation version 2.0 needs to be
enabled.
TEST=Build pass and timestamp is not reset in ATF and payload
BUG=b:343881008
Change-Id: I520986b81ca153ec3ce56558a80619448cfc0c59
Signed-off-by: Zhanzhan Ge <zhanzhan.ge@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83928
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Mediatek SoCs start operating at eMMC clock around 3MHz right after
power-on due to wrong src_hz value. In JEDEC spec, eMMC clock needs
under 400kHz.
When we need to set a clock output frequency, we actually set a
frequency division value. Originally, we set the source clock
frequency to 50MHz, the target frequency to 400KHz, and get the
division value 128. However, the actual source clock frequency is
400MHz, so the final actual output is 400MHz/128=3.125MHz.
So we correct source clock frequency to 400MHz for eMMC output
clock of 400KHz.
BUG=b:356578805
TEST=test boot ok; measure eMMC clock ok; no boot time impact
Change-Id: I9c8836b23fb21e9b0bdc80fbe85142ea0fa5e381
Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.corp-partner.google.com>
Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84298
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
De-assert PERST# at romstage to reduce the waiting time in ramstage.
Before
```
[INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done,
de-assert PERST# now
[INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries)
```
After
```
[INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done,
de-assert PERST# now
[DEBUG] wait_perst_asserted: 457568 us elapsed since assert PERST#
[DEBUG] wait_perst_done: 163413 us elapsed since de-assert PERST#
[INFO ] mtk_pcie_domain_enable: PCIe link up success (1 tries)
```
BUG=none
TEST=boot from NVMe
Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84118
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Even we assert PRSET# early to save the delay between PERST# assertion
and de-assertion. MediaTek PCIe driver still takes 47ms waiting for PCIe
link up. (1ms delay for each try)
```
[INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries)
```
Refactor common/pcie.c and add mtk_pcie_deassert_perst for early PCIe
reset. So we can de-assert PERST# at early stage to improve the boot
time.
BUG=b:361728592
TEST=emerge-cherry coreboot
Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84117
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
mtk_pcie_reset can be shared with MT8196. So move it to common/pcie.c.
BUG=b:361728592
TEST=emerge-cherry coreboot
Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Currently pcie.c is built into ramstage only, where DEVTREE_CONST is an
empty macro, so there's no problem with that. However, if we would like
to include that file in pre-ramstage, then DEVTREE_CONST would be
'const', leading to the following build error:
```
src/soc/mediatek/common/pcie.c:104:26: error: assignment discards
'const' qualifier from pointer target type [-Werror=discarded-qualifiers]
104 | root_dev = pcidev_path_on_root(devfn);
| ^
```
BUG=none
TEST=emerge-cherry coreboot
Change-Id: Ia7c95424019ec0dca50bbc6be7f81b6180d06d6e
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84113
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
