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soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c

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mtk_pcie_reset can be shared with MT8196. So move it to common/pcie.c.

BUG=b:361728592
TEST=emerge-cherry coreboot

Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Yidi Lin 2024-08-27 16:05:05 +08:00 • committed by Felix Held
commit 62632ebf24
5 changed files with 15 additions and 26 deletions
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1
src/soc/mediatek/common/include/soc/pcie_common.h
View file

@ -22,5 +22,6 @@ struct mtk_pcie_config {
void mtk_pcie_domain_read_resources(struct device *dev);
void mtk_pcie_domain_set_resources(struct device *dev);
void mtk_pcie_domain_enable(struct device *dev);
void mtk_pcie_reset(uintptr_t base_reg, bool enable);
#endif

14
src/soc/mediatek/common/pcie.c
View file

@ -247,6 +247,16 @@ void mtk_pcie_domain_set_resources(struct device *dev)
pci_domain_set_resources(dev);
}
void mtk_pcie_reset(uintptr_t base_reg, bool enable)
{
uint32_t flags = PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
if (enable)
setbits32p(base_reg + PCIE_RST_CTRL_REG, flags);
else
clrbits32p(base_reg + PCIE_RST_CTRL_REG, flags);
}
enum cb_err fill_lb_pcie(struct lb_pcie *pcie)
{
if (!pci_root_bus())
@ -291,7 +301,7 @@ void mtk_pcie_domain_enable(struct device *dev)
printk(BIOS_WARNING,
"%s: PCIe early init data not found, sleeping 100ms\n",
__func__);
mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, true);
mtk_pcie_reset(conf->base, true);
} else {
printk(BIOS_WARNING,
"%s: Need an extra %ld us delay to meet PERST# deassertion requirement\n",
@ -302,7 +312,7 @@ void mtk_pcie_domain_enable(struct device *dev)
}
/* De-assert reset signals */
mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, false);
mtk_pcie_reset(conf->base, false);
if (!retry(100,
(tries++, read32p(conf->base + PCIE_LINK_STATUS_REG) &

2
src/soc/mediatek/mt8195/Makefile.mk
View file

@ -13,7 +13,7 @@ bootblock-y += bootblock.c
bootblock-y += ../common/early_init.c
bootblock-y += ../common/eint_event.c
bootblock-y += ../common/mmu_operations.c
bootblock-$(CONFIG_PCI) += pcie.c
bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c
bootblock-y += ../common/pll.c pll.c
bootblock-y += ../common/tracker.c ../common/tracker_v2.c
bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c

1
src/soc/mediatek/mt8195/include/soc/pcie.h
View file

@ -6,7 +6,6 @@
#include <soc/pcie_common.h>
#include <types.h>
void mtk_pcie_reset(uintptr_t reg, bool enable);
void mtk_pcie_pre_init(void);
bool mainboard_needs_pcie_init(void);

23
src/soc/mediatek/mt8195/pcie.c
View file

@ -9,11 +9,6 @@
#include <soc/pcie_common.h>
#define PCIE_REG_BASE_PORT0 0x112f0000
#define PCIE_RST_CTRL_REG (PCIE_REG_BASE_PORT0 + 0x148)
#define PCIE_MAC_RSTB BIT(0)
#define PCIE_PHY_RSTB BIT(1)
#define PCIE_BRG_RSTB BIT(2)
#define PCIE_PE_RSTB BIT(3)
struct pad_func {
gpio_t gpio;
@ -46,28 +41,12 @@ static void mtk_pcie_set_pinmux(uint8_t port)
}
}
void mtk_pcie_reset(uintptr_t reg, bool enable)
{
uint32_t val;
val = read32p(reg);
if (enable)
val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
PCIE_PE_RSTB;
else
val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |
PCIE_PE_RSTB);
write32p(reg, val);
}
void mtk_pcie_pre_init(void)
{
mtk_pcie_set_pinmux(0);
/* Assert all reset signals at early stage */
mtk_pcie_reset(PCIE_RST_CTRL_REG, true);
mtk_pcie_reset(PCIE_REG_BASE_PORT0, true);
early_init_save_time(EARLY_INIT_PCIE);
}