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soc/mediatek/common: Move common GPIO definitions to gpio_defs.h

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BUG=none
TEST=emerge-{asurada, cherry, corsola, geralt, rauru} coreboot

Change-Id: If35dcc4d88732f92c7c43a5eed0478ec52cf1802
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84221
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Yidi Lin 2024-09-05 12:22:36 +08:00 • committed by Felix Held
commit 56e0ceb2c7
6 changed files with 69 additions and 199 deletions
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44
src/soc/mediatek/common/include/soc/gpio_defs.h Normal file
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@ -0,0 +1,44 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef SOC_MEDIATEK_COMMON_GPIO_DEFS_H
#define SOC_MEDIATEK_COMMON_GPIO_DEFS_H
#include <types.h>
enum {
MAX_GPIO_REG_BITS = 32,
MAX_GPIO_MODE_PER_REG = 8,
GPIO_MODE_BITS = 4,
};
#define GPIO(name) ((gpio_t){ \
.id = PAD_##name##_ID, \
.flag = PAD_##name##_FLAG, \
.bit = PAD_##name##_BIT, \
.base = PAD_##name##_BASE, \
.offset = PAD_##name##_OFFSET \
})
#define PIN(id, name, flag, bit, base, offset, \
func1, func2, func3, func4, func5, func6, func7) \
PAD_##name##_ID = id, \
PAD_##name##_FLAG = flag, \
PAD_##name##_BIT = bit, \
PAD_##name##_BASE = base, \
PAD_##name##_OFFSET = offset, \
PAD_##name##_FUNC_##func1 = 1, \
PAD_##name##_FUNC_##func2 = 2, \
PAD_##name##_FUNC_##func3 = 3, \
PAD_##name##_FUNC_##func4 = 4, \
PAD_##name##_FUNC_##func5 = 5, \
PAD_##name##_FUNC_##func6 = 6, \
PAD_##name##_FUNC_##func7 = 7
struct gpio_val_regs {
uint32_t val;
uint32_t set;
uint32_t rst;
uint32_t align;
};
#endif

45
src/soc/mediatek/mt8186/include/soc/gpio.h
View file

@ -10,41 +10,13 @@
#include <soc/addressmap.h>
#include <soc/gpio_common.h>
#include <soc/gpio_defs.h>
#include <types.h>
#define GPIO_NUM 185
enum {
MAX_GPIO_REG_BITS = 32,
MAX_GPIO_MODE_PER_REG = 8,
GPIO_MODE_BITS = 4,
};
#define GPIO_ID(name) PAD_##name##_ID
#define PIN(id, name, flag, bit, base, offset, \
func1, func2, func3, func4, func5, func6, func7) \
PAD_##name##_ID = id, \
PAD_##name##_FLAG = flag, \
PAD_##name##_BIT = bit, \
PAD_##name##_BASE = base, \
PAD_##name##_OFFSET = offset, \
PAD_##name##_FUNC_##func1 = 1, \
PAD_##name##_FUNC_##func2 = 2, \
PAD_##name##_FUNC_##func3 = 3, \
PAD_##name##_FUNC_##func4 = 4, \
PAD_##name##_FUNC_##func5 = 5, \
PAD_##name##_FUNC_##func6 = 6, \
PAD_##name##_FUNC_##func7 = 7
#define GPIO(name) ((gpio_t){ \
.id = PAD_##name##_ID, \
.flag = PAD_##name##_FLAG, \
.bit = PAD_##name##_BIT, \
.base = PAD_##name##_BASE, \
.offset = PAD_##name##_OFFSET \
})
enum {
PIN(0, EINT0, 0, 13, 0x16, 0x50,
I2S0_MCK, SPI0_CLK_B, I2S2_MCK, CMFLASH0,
@ -603,21 +575,14 @@ enum {
RES5, RES6, RES7),
};
struct val_regs {
uint32_t val;
uint32_t set;
uint32_t rst;
uint32_t align;
};
struct gpio_regs {
struct val_regs dir[7];
struct gpio_val_regs dir[7];
uint8_t rsv00[144];
struct val_regs dout[7];
struct gpio_val_regs dout[7];
uint8_t rsv01[144];
struct val_regs din[7];
struct gpio_val_regs din[7];
uint8_t rsv02[144];
struct val_regs mode[28];
struct gpio_val_regs mode[28];
uint8_t rsv03[560];
uint32_t dram_pinmux_trapping;
};

44
src/soc/mediatek/mt8188/include/soc/gpio.h
View file

@ -10,39 +10,11 @@
#include <soc/addressmap.h>
#include <soc/gpio_common.h>
#include <soc/gpio_defs.h>
#include <types.h>
#define GPIO_NUM 177
enum {
MAX_GPIO_REG_BITS = 32,
MAX_GPIO_MODE_PER_REG = 8,
GPIO_MODE_BITS = 4,
};
#define PIN(id, name, flag, bit, base, offset, \
func1, func2, func3, func4, func5, func6, func7) \
PAD_##name##_ID = id, \
PAD_##name##_FLAG = flag, \
PAD_##name##_BIT = bit, \
PAD_##name##_BASE = base, \
PAD_##name##_OFFSET = offset, \
PAD_##name##_FUNC_##func1 = 1, \
PAD_##name##_FUNC_##func2 = 2, \
PAD_##name##_FUNC_##func3 = 3, \
PAD_##name##_FUNC_##func4 = 4, \
PAD_##name##_FUNC_##func5 = 5, \
PAD_##name##_FUNC_##func6 = 6, \
PAD_##name##_FUNC_##func7 = 7
#define GPIO(name) ((gpio_t){ \
.id = PAD_##name##_ID, \
.flag = PAD_##name##_FLAG, \
.bit = PAD_##name##_BIT, \
.base = PAD_##name##_BASE, \
.offset = PAD_##name##_OFFSET \
})
enum {
PIN(0, GPIO00, 0, 6, 0x31, 0xe0,
TP_GPIO0_AO, SPIM5_CSB, UTXD1, DMIC3_CLK,
@ -577,20 +549,14 @@ enum {
RES5, RES6, RES7),
};
struct val_regs {
uint32_t val;
uint32_t set;
uint32_t rst;
uint32_t align;
};
struct gpio_regs {
struct val_regs dir[7];
struct gpio_val_regs dir[7];
uint8_t rsv00[144];
struct val_regs dout[7];
struct gpio_val_regs dout[7];
uint8_t rsv01[144];
struct val_regs din[7];
struct gpio_val_regs din[7];
uint8_t rsv02[144];
struct val_regs mode[28];
struct gpio_val_regs mode[28];
uint8_t rsv03[560];
uint32_t dram_pinmux_trapping;
};

45
src/soc/mediatek/mt8192/include/soc/gpio.h
View file

@ -5,37 +5,9 @@
#include <soc/addressmap.h>
#include <soc/gpio_common.h>
#include <soc/gpio_defs.h>
#include <types.h>
enum {
MAX_GPIO_REG_BITS = 32,
MAX_GPIO_MODE_PER_REG = 8,
GPIO_MODE_BITS = 4,
};
#define PIN(id, name, flag, bit, base, offset, \
func1, func2, func3, func4, func5, func6, func7) \
PAD_##name##_ID = id, \
PAD_##name##_FLAG = flag, \
PAD_##name##_BIT = bit, \
PAD_##name##_BASE = base, \
PAD_##name##_OFFSET = offset, \
PAD_##name##_FUNC_##func1 = 1, \
PAD_##name##_FUNC_##func2 = 2, \
PAD_##name##_FUNC_##func3 = 3, \
PAD_##name##_FUNC_##func4 = 4, \
PAD_##name##_FUNC_##func5 = 5, \
PAD_##name##_FUNC_##func6 = 6, \
PAD_##name##_FUNC_##func7 = 7
#define GPIO(name) ((gpio_t){ \
.id = PAD_##name##_ID, \
.flag = PAD_##name##_FLAG, \
.bit = PAD_##name##_BIT, \
.base = PAD_##name##_BASE, \
.offset = PAD_##name##_OFFSET \
})
enum {
PIN(0, EINT0, 0, 9, 0x23, 0xb0,
SPI6_CLK, I2S5_MCK, PWM_0, TDM_LRCK,
@ -699,21 +671,14 @@ enum {
I2S6_DI, I2S8_DI, RES6, RES7),
};
struct val_regs {
uint32_t val;
uint32_t set;
uint32_t rst;
uint32_t align;
};
struct gpio_regs {
struct val_regs dir[7];
struct gpio_val_regs dir[7];
uint8_t rsv00[144];
struct val_regs dout[7];
struct gpio_val_regs dout[7];
uint8_t rsv01[144];
struct val_regs din[7];
struct gpio_val_regs din[7];
uint8_t rsv02[144];
struct val_regs mode[28];
struct gpio_val_regs mode[28];
uint8_t rsv03[560];
uint32_t dram_pinmux_trapping;
};

45
src/soc/mediatek/mt8195/include/soc/gpio.h
View file

@ -5,37 +5,9 @@
#include <soc/addressmap.h>
#include <soc/gpio_common.h>
#include <soc/gpio_defs.h>
#include <types.h>
enum {
MAX_GPIO_REG_BITS = 32,
MAX_GPIO_MODE_PER_REG = 8,
GPIO_MODE_BITS = 4,
};
#define PIN(id, name, flag, bit, base, offset, \
func1, func2, func3, func4, func5, func6, func7) \
PAD_##name##_ID = id, \
PAD_##name##_FLAG = flag, \
PAD_##name##_BIT = bit, \
PAD_##name##_BASE = base, \
PAD_##name##_OFFSET = offset, \
PAD_##name##_FUNC_##func1 = 1, \
PAD_##name##_FUNC_##func2 = 2, \
PAD_##name##_FUNC_##func3 = 3, \
PAD_##name##_FUNC_##func4 = 4, \
PAD_##name##_FUNC_##func5 = 5, \
PAD_##name##_FUNC_##func6 = 6, \
PAD_##name##_FUNC_##func7 = 7
#define GPIO(name) ((gpio_t){ \
.id = PAD_##name##_ID, \
.flag = PAD_##name##_FLAG, \
.bit = PAD_##name##_BIT, \
.base = PAD_##name##_BASE, \
.offset = PAD_##name##_OFFSET \
})
enum {
PIN(0, GPIO_00, 1, 0, 0x23, 0x60,
TP_GPIO0_AO, MSDC2_CMD, TDMIN_MCK, CLKM0,
@ -470,21 +442,14 @@ enum {
RES5, RES6, DBG_MON_A13),
};
struct val_regs {
uint32_t val;
uint32_t set;
uint32_t rst;
uint32_t align;
};
struct gpio_regs {
struct val_regs dir[7];
struct gpio_val_regs dir[7];
uint8_t rsv00[144];
struct val_regs dout[7];
struct gpio_val_regs dout[7];
uint8_t rsv01[144];
struct val_regs din[7];
struct gpio_val_regs din[7];
uint8_t rsv02[144];
struct val_regs mode[28];
struct gpio_val_regs mode[28];
uint8_t rsv03[560];
uint32_t dram_pinmux_trapping;
};

45
src/soc/mediatek/mt8196/include/soc/gpio.h
View file

@ -10,54 +10,19 @@
#include <soc/addressmap.h>
#include <soc/gpio_common.h>
#include <soc/gpio_defs.h>
#include <types.h>
#define GPIO_NUM 271
enum {
MAX_GPIO_REG_BITS = 32,
MAX_GPIO_MODE_PER_REG = 8,
GPIO_MODE_BITS = 4,
};
struct val_regs {
uint32_t val;
uint32_t set;
uint32_t rst;
uint32_t align;
};
struct gpio_regs {
struct val_regs dir[16];
struct val_regs dout[16];
struct val_regs din[16];
struct val_regs mode[32];
struct gpio_val_regs dir[16];
struct gpio_val_regs dout[16];
struct gpio_val_regs din[16];
struct gpio_val_regs mode[32];
uint32_t dram_pinmux_trapping;
};
#define PIN(id, name, flag, bit, base, offset, \
func1, func2, func3, func4, func5, func6, func7) \
PAD_##name##_ID = id, \
PAD_##name##_FLAG = flag, \
PAD_##name##_BIT = bit, \
PAD_##name##_BASE = base, \
PAD_##name##_OFFSET = offset, \
PAD_##name##_FUNC_##func1 = 1, \
PAD_##name##_FUNC_##func2 = 2, \
PAD_##name##_FUNC_##func3 = 3, \
PAD_##name##_FUNC_##func4 = 4, \
PAD_##name##_FUNC_##func5 = 5, \
PAD_##name##_FUNC_##func6 = 6, \
PAD_##name##_FUNC_##func7 = 7
#define GPIO(name) ((gpio_t){ \
.id = PAD_##name##_ID, \
.flag = PAD_##name##_FLAG, \
.bit = PAD_##name##_BIT, \
.base = PAD_##name##_BASE, \
.offset = PAD_##name##_OFFSET \
})
enum {
PIN(0, EINT0, 0, 0, 0x18, 0xa0,
DMIC1_CLK, RES2, SPI3_A_MO, FMI2S_B_LRCK,