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soc/mediatek/common/pcie: Use clr/setbits32p

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Use clr/setbits32p to make code cleaner.

BUG=none
TEST=emerge-cherry coreboot

Change-Id: Id99d5aafdf4d687dbe3a0bef29b148537cf58dd8
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
This commit is contained in:
Yidi Lin 2024-08-27 13:19:35 +08:00 • committed by Felix Held
commit 7c71b94984
1 changed files with 4 additions and 10 deletions
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14
src/soc/mediatek/common/pcie.c
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@ -266,20 +266,14 @@ void mtk_pcie_domain_enable(struct device *dev)
uint32_t val;
/* Set as RC mode */
val = read32p(conf->base + PCIE_SETTING_REG);
val |= PCIE_RC_MODE;
write32p(conf->base + PCIE_SETTING_REG, val);
setbits32p(conf->base + PCIE_SETTING_REG, PCIE_RC_MODE);
/* Set class code */
val = read32p(conf->base + PCIE_PCI_IDS_1);
val &= ~GENMASK(31, 8);
val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8);
write32p(conf->base + PCIE_PCI_IDS_1, val);
clrsetbits32p(conf->base + PCIE_PCI_IDS_1, GENMASK(31, 8),
PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8));
/* Mask all INTx interrupts */
val = read32p(conf->base + PCIE_INT_ENABLE_REG);
val &= ~PCIE_INTX_ENABLE;
write32p(conf->base + PCIE_INT_ENABLE_REG, val);
clrbits32p(conf->base + PCIE_INT_ENABLE_REG, PCIE_INTX_ENABLE);
perst_time_us = early_init_get_elapsed_time_us(EARLY_INIT_PCIE);
printk(BIOS_DEBUG, "%s: %ld us elapsed since assert PERST#\n",