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mb/google/cherry: Complete PCIe reset in romstage

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De-assert PERST# at romstage to reduce the waiting time in ramstage.

Before
```
[INFO ]  wait_perst_done: PCIe early PERST# de-assertion is not done,
de-assert PERST# now
[INFO ]  mtk_pcie_domain_enable: PCIe link up success (47 tries)
```
After
```
[INFO ]  wait_perst_done: PCIe early PERST# de-assertion is not done,
de-assert PERST# now
[DEBUG]  wait_perst_asserted: 457568 us elapsed since assert PERST#
[DEBUG]  wait_perst_done: 163413 us elapsed since de-assert PERST#
[INFO ]  mtk_pcie_domain_enable: PCIe link up success (1 tries)
```

BUG=none
TEST=boot from NVMe

Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84118
Reviewed-by: Jianjun Wang <jianjun.wang@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Yidi Lin 2024-08-28 17:15:36 +08:00 • committed by Felix Held
commit 3d5ff65b27
2 changed files with 4 additions and 0 deletions
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3
src/mainboard/google/cherry/romstage.c
View file

@ -8,6 +8,7 @@
#include <soc/mt6315.h>
#include <soc/mt6359p.h>
#include <soc/mt6360.h>
#include <soc/pcie.h>
#include <soc/pll_common.h>
#include <soc/pmif.h>
#include <soc/rtc.h>
@ -33,6 +34,8 @@ void platform_romstage_main(void)
mt6360_init(I2C7);
clk_buf_init();
rtc_boot();
if (CONFIG(PCI))
mtk_pcie_deassert_perst();
mtk_dram_init();
scp_rsi_enable();
}

1
src/soc/mediatek/mt8195/Makefile.mk
View file

@ -36,6 +36,7 @@ romstage-y += ../common/mt6315.c mt6315.c
romstage-y += ../common/mt6359p.c mt6359p.c
romstage-y += mt6360.c
romstage-y += mt6691.c
romstage-$(CONFIG_PCI) += ../common/early_init.c ../common/pcie.c
romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
ramstage-y += apusys.c