Move CPU init closer to other SoC and CPX.
FSP-S only is aware of socket 0, thus all cores must rerun all
settings already done by FSP, in order to set up socket 1 as well.
FSP sets the following on socket0:
- Set BIT20 in MSR_VR_MISC_CONFIG
- Set LTR_IIO_DISABLE in MSR_POWER_CTL
Lock the following MSRs:
- MSR_SNC_CONFIG
- MSR_CONFIG_TDP_CONTROL
- MSR_FEATURE_CONFIG
- MSR_TURBO_ACTIVATION_RATIO
Also do the following as done on other SoCs:
- Configure VMX and lock it
- Enable LAPIC TPRs (fixes MWAIT support)
- Honor CONFIG_SET_MSR_AESNI_LOCK_BIT
- Set TCC thermal target as set in devicetree
Fixes 8 second wakeup time from LAPIC interrupts when in MWAIT.
TEST: Booted on ocp/tiogapass to Linux 6.9 with all cores in
ACPI C6, no boot delay or hung tasks could be found.
Change-Id: If08ef5150b104b0c2329fcb64a0476ce641c831c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85289
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On platforms with multiple IOAPICs the GSI base must not be
linear, which is currently assumed by acpi_create_madt_ioapic_from_hw().
Integrate the existing struct device DEVICE_PATH_IOAPIC type and allow
to assign custom GSI bases for each IOAPIC. Write out the IOAPIC devices
into the MADT table if any.
For now, since no platform adds IOAPIC devices, the existing behaviour
remains the same. Allows to get rid of soc_get_ioapic_info().
Change-Id: Ie13d4f5c4f0704f0935974f90e5b7cf24e94aab3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The CSE MKHI_BUP_COMMON_GET_BOOT_PERF_DATA command is also implemented
in non-Lite CSE SKUs. Original CL [1] adding this feature also says
that, but at that point the feature was validated for CSE Lite only.
Move cse_get_boot_performance_data() to shared blk/cse/telemetry.c to
have it compile for mainboards without CSE Lite.
TEST=Boot NovaCustom V540TU (MTL-P / ME Consumer) with
SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 selected and check `cbmem -t`:
990:CSME ROM started execution 0
944:CSE sent 'Boot Stall Done' to PMC 34,000
945:CSE started to handle ICC configuration 172,000 (138,000)
946:CSE sent 'Host BIOS Prep Done' to PMC 172,000 (0)
947:CSE received 'CPU Reset Done Ack sent' from PMC 314,000 (142,000)
991:Die Management Unit (DMU) load completed 360,000 (46,000)
0:1st timestamp 385,844 (25,844)
11:start of bootblock 398,796 (12,952)
12:end of bootblock 402,099 (3,302)
[...]
[1]: https://review.coreboot.org/c/coreboot/+/59507
Change-Id: I3a5b1abd282af9af33cef2371719df4133684a2e
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
This change fixes building NovaCustom V540TU, which previously errored
out due to missing MISCCFG_GPIO_PM_CONFIG_BITS definition.
Replace soc/gpio_defs.h with gpio.h which includes everything we need,
same as it was done for ADL in change 71266, and other SoCs.
TEST=Build and boot NovaCustom V540TU
Change-Id: I52a495f696258fc63752dd8e66e318e144bb768e
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This change adds soundwire codec addresses in the devicetree to
calculate addresses for the ACPI table instead of previous kconfig which
allows single board to select multiple soundwire codecs at runtime
based on FW_CONFIG.
BUG=b:368495490
TEST=build coreboot image and boot on google fatcat. Disassemble
SSDT and confirm ACPI entries are correct for alc7xx device.
Change-Id: I3322ae2d106d3628dbf627aacf999056d82ee7a9
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Signed-off-by: Naveen M <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85440
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
- Use common config DRIVERS_SOUNDWIRE_ALC_BASE_7XX for ALC7xx variants
- Introduce soundwire codec address in soundwire chip.h to calculate
device address for acpi table based on overridetree.
- Update devicetree and Kconfig to use common config.
BUG=b:368495490
TEST=build coreboot image and boot on Intel RVP board. Disassemble
SSDT and confirm ACPI entries are correct for alc7xx device.
Change-Id: I5953d0fcb7b15368888901f88c5616757ac42877
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Signed-off-by: Naveen M <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85282
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch updates the flash layout for Fatcat variants to ensure
the flash layout is in alignment with the previous generation CrOS
devices like Rex.
SI_ALL: 9MB -> 8MB
SI_BIOS: 23MB -> 24MB
BUG=b:382247229
TEST=Able to build and boot google/fatcat.
Change-Id: I716fae09dee0c05b8b840dc80647d7959aa03a50
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit enhances the SMBIOS Type 4 table by populating the "serial
number" field with the unique SoC QDF information retrieved via PMC
IPC.
This improvement provides more accurate and detailed processor
information for Panther Lake SoCs and onwards, aiding in:
- System identification
- Diagnostics
- Asset management
Previously, the serial number field was not populated.
TEST=Able to build and boot google/fatcat.
Example of SMBIOS Type 4 output:
Before this commit:
Serial Number: Not Specified
Asset Tag: Not Specified
Part Number: Not Specified
After this commit:
Serial Number: ABCD (Example SoC QDF information)
Asset Tag: Not Specified
Part Number: Not Specified
Change-Id: I38a0bb0e44c619393b8f058ae30fbf2f9719b724
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit introduces a new function,
`retrieve_soc_qdf_info_via_pmc_ipc()`, to retrieve the SoC QDF
information string using the PMC IPC mechanism.
This function allows for more flexible use of the SoC QDF information,
enabling its use in various data structures like the SMBIOS Type 4
table.
The existing `pmc_dump_soc_qdf_info()` function is updated to use this
new function to retrieve the QDF information before printing it.
TEST=Able to build and boot google/fatcat.
Change-Id: I91ccf8aae4be9e9bbcad8ef2f422b88edef66376
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Add the MEMMAP_DIMM_DEVICE_INFO_STRUCT for skylake_sp and let common
code fill in the SMBIOS type 17 entries for all slots and found DIMMs.
This also allows to build dimm.c unconditionally on all xeon_sp socs.
Test: On ocp/tiogapass all DIMMs and slots are visible in SMBIOS.
Change-Id: I686b1e3ef946240785111f86a5f23a109a6a52ad
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Fix debug prints that use non-thread safe dev_path(). Since the code
is part of MPinit, it's using multiple threads and one threads modifies
the only buffer used, resulting in path being printed that do not belong
to the current thread.
Drop the call since printing the APIC ID is sufficient and thread safe.
Change-Id: I0cbc9cb11da8397ab6c2e8e56414558a8a0db93b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85288
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On 1st and 2nd gen Xeon-SP the VTD PCI device has different PCI IDs,
depending if it's on the CSTACK or PSTACK.
Make sure to handle all VTD device on all stacks the same.
For later SoCs this was already the case since the PCI devices have
the same PCI ID.
Change-Id: I0d726b5ae620282dd4c9036d536e5e51d19a0a0b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Include stddef.h to fix the compiler error when using ipmi_ocp.h:
src/drivers/ipmi/ocp/ipmi_ocp.h:199:44: error: unknown type name 'size_t'
Change-Id: Iccd131295263460a4939e51e12ece87ea22c417c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85317
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a new config to libpayload whose sole purpose it is to
be as different as possible from the defconfig, in order to try to get
the CI to exercise more code paths and thus catch more issues.
Change-Id: Ia6bd7572056b7a02acb686542810e661e015cc69
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
According to the FDT specification the FDT_END token is supposed to be
the last token in the structure block, not a free-floating token
immediately outside of it. That means we're supposed to count it in
struct_size. It seems that the kernel never cared about this, but some
FDT parsing utilities like `fdtgrep` do.
Change-Id: Icdeadbeefcafed00dbabefeed1337c0debc86836
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85462
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Print the current project version in the console and in the generated
file with the pad configuration. This makes support easier, since we
know which version of the utility was used and whether we need to
re-generate the configuration file if an error was made in the latest
changes in the code. The version string includes several parts:
{major}.{minor}-{last commit in the intelp2m directory}-{?dirty}
The major is incremented if a new platform is added, minor - if changes
in functionality are made. Add dirty if the changes were not taken into
account using git.
Use the following command to print the version:
make version
Change-Id: Id2fd0757c003004af976309a44dbbfff0eb517a7
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67321
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- The generated map of long and short macros should correspond to the
reference ones for all pads (INTEL-SUNRISE-PCH/PAD-MAP). The test
suite is based on the generated macros of a real platform.
- generated field macros should correspond to the RO_FIELDS mask
(INTEL-SUNRISE-PCH/MASK);
- macros generated from the zero values bits of the DW registers should
correspond to the reference ones (INTEL-SUNRISE-PCH/EMRTY).
Use the following command in the console to run all the tests in the
project:
make test
Change-Id: I15c7483f120a330849d4bad036427be205b0911c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
- The generated map of long and short macros should correspond to the
reference ones for all pads (INTEL-LEWISBURG-PCH/PAD-MAP). The test
suite is based on the generated macros of a real platform.
- generated field macros should correspond to the RO_FIELDS mask
(INTEL-LEWISBURG-PCH/MASK);
- macros generated from the zero values bits of the DW registers should
correspond to the reference ones (INTEL-LEWISBURG-PCH/EMRTY).
Change-Id: Iec18462be8428c3f37d546332211a730ee589a2d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67133
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
- The generated map of long and short macros should correspond to
the reference ones for all pads (INTEL-APOLLO-PCH/PAD-MAP). The
test suite is based on the generated macros of a real platform.
- generated field macros should correspond to the RO_FIELDS mask
(INTEL-APOLLO-PCH/MASK);
- macros generated from the zero values bits of the DW registers
should correspond to the reference ones (INTEL-APOLLO-PCH/EMRTY).
Change-Id: I1c47edb31d24930068486c74147c5fbc9b18b4b6
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67134
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generally the base address of FSP output is already aligned so there is
no need to minus 1. The current code loses 1 byte in the lower DRAM
address space.
Change-Id: Ia8147702aad496c431cf10b896d68a826c9e45b1
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85434
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Add the support RAM parts for uldrenite.
Here is the ram part number list:
DRAM Part Name ID to assign
H9JCNNNBK3MLYR-N6E 0 (0000)
K3KL6L60GM-MGCT 1 (0001)
K3KL8L80CM-MGCT 2 (0010)
MT62F1G32D2DS-026 WT:B 2 (0010)
H58G56CK8BX146 3 (0011)
BUG=b:380789023
BRANCH=None
TEST=emerge-nissa coreboot
Change-Id: I8003f693e1d8fa049a0e508078ce29b5bb39f2ef
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Create the pujjogatwin variant of nissa reference board by copying the
pujjoga files to a new directory named for the variant.
The difference between pujjoga and pujjogatwin is that pujjogatwin use
Twin Lake CPU and firmware config, so copying the pujjoga setting files
to create new variant.
BUG=b:381152086
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PUJJOGATWIN
Change-Id: I345ce463699840b10016555bb104a16968e7a8c1
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85329
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Linux upstream's checkpatch.pl has a default max line length of 100.
Since coreboot uses 96, add --max-line-length=96 to the config file.
Change-Id: I7737f3d2e0d016b0f0dd82df2865a6b51b667066
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85435
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SoC won't be able to boot without dram.elf. Therefore, we should
always expect the file to exist in build time.
BUG=none
TEST=emerge-rauru coreboot
BRANCH=none
Change-Id: Ib902dc4778f34a144dddf847c283fe77d4c776f6
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85441
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This matches the size used in the reference code and required by the
corresponding document #55758 Rev. 2.04. This doesn't seem to make any
difference in runtime behavior, but I'd rather waste a kilobyte of SMM
RAM, than debugging possible problems caused from not following the
corresponding specification.
Change-Id: I2ee30d6d1255317efcd3960016069dfe50885aa7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
While gcc didn't seem to care about that mismatch, clang didn't like
that '%ld' was used in the printk format string to print a size_t
variable. Replace the correct '%zu' instead of '%ld' to fix that.
Change-Id: I32bc584abe835c9c1d732c12311881345b8f0cdf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85251
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To see if things went wrong in the 'handle_psp_command' function, print
the status code in case it's not MBOX_PSP_SUCCESS.
Change-Id: I8c02e8e29ab5619282e5b864a8cea6f0703f6ef2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85238
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extend the 'psp_smi_spi_rpmc_inc_mc' and 'psp_smi_spi_rpmc_req_mc'
function stubs that now implement the actual functionality by calling
'spi_flash_rpmc_increment' and 'spi_flash_rpmc_request' after doing some
sanity checks.
TEST=When selecting both 'SOC_AMD_COMMON_BLOCK_PSP_RPMC' and
'SOC_AMD_COMMON_BLOCK_PSP_SMI' Kconfig options on a board with an RPMC-
capable SPI flash, the PSP SMI handler can successfully service not only
the already working SPI flash write command, but also the increment
monotonic counter RPMC command:
[NOTE ] coreboot-[...] x86_32 smm starting (log level: 8)...
[SPEW ] SMI# #0
[SPEW ] PSP: SPI write request
[DEBUG] FMAP: area PSP_NVRAM found @ f20000 (131072 bytes)
[SPEW ] PSP: SPI write 0x400 bytes at 0x0
[NOTE ] coreboot-[...] x86_32 smm starting (log level: 8)...
[SPEW ] SMI# #0
[SPEW ] PSP: SPI write request
[DEBUG] FMAP: area PSP_NVRAM found @ f20000 (131072 bytes)
[SPEW ] PSP: SPI write 0x400 bytes at 0x400
[NOTE ] coreboot-[...] x86_32 smm starting (log level: 8)...
[SPEW ] SMI# #8
[SPEW ] PSP: SPI write request
[DEBUG] FMAP: area PSP_NVRAM found @ f20000 (131072 bytes)
[SPEW ] PSP: SPI write 0x310 bytes at 0x800
[NOTE ] coreboot-[...] x86_32 smm starting (log level: 8)...
[SPEW ] SMI# #1
[SPEW ] PSP: SPI write request
[DEBUG] FMAP: area PSP_RPMC_NVRAM found @ f40000 (262144 bytes)
[SPEW ] PSP: SPI write 0x70 bytes at 0x100
[NOTE ] coreboot-[...] x86_32 smm starting (log level: 8)...
[SPEW ] SMI# #0
[SPEW ] PSP: SPI RPMC increment monotonic counter request
This requires the PSP_RPMC_NVRAM FMAP section to have the correct size
which in case of Renoir is 256 kByte. Having this large enough size also
makes the PSP report that the PSP RPMC NVRAM is healthy which wasn't the
case in previous tests when the region was too small.
Change-Id: I20e4f60d4e35d33e560fc43212b320e817e13004
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84906
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Commit ee93b35bc3 ("soc/amd/common/psp_smi_flash: add RPMC command-
specific data structures") added the 'psp_spi_rpmc_inc_mc' and
'psp_smi_rpmc_req_mc' structs, but added the counter data as uint32_t
while it should have been an array of 4 uint8_t, since the bytes in that
buffer are already in the order in which they need to be sent over to
the SPI flash which is different than the byte order of a uint32_t. This
was only noticed after getting the code that uses these structs was
tested.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6c290535a1896c080b74d892cb289e6e122d4525
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85236
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add functions to send the RPMC-related commands to a RPMC-capable SPI
flash to provision the root key, update the HMAC key, increment the
monotonic counter, and request the monotonic counter data. To talk to
the flash chip, the command bytes and polling mechanism described in the
SFDP data structure of the flash are used.
The JESD260 specification was used as a reference.
Some of inspiration was taken from
github.com/teslamotors/coreboot/tree/tesla-4.12-amd
TEST=When used with the later patch that calls some of the functions
added in this patch, sending the RPMC increment monotonic counter
command to the RPMC-capable SPI flash, in this case W74M12JW, is
successful.
Change-Id: Ia9bd69d0105c66bf5ecb6c90e8c782a81912bd40
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84837
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add information about how the symlink target can be used
to develop and test additions to the coreboot tree from
site-local.
Change-Id: I75f9e9575005e9ee2f255848a21c5e57c30e9e72
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
The parentheses are missing in the mtk_scp macro definition.
The only usage is
SET32_BITFIELDS(&mtk_scp->scp_clk_on_ctrl,
SCP_CLK_ON_CTRL, 1);
I guess that bit is already set by default, so there's no ULPOSC clock
issue found so far.
BUG=none
TEST=none
BRANCH=cherry
Change-Id: I2dbb5c465ee60f0c4dce8ff77b8d3a39db42e4f5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Derive the audio amplifier from FW_CONFIG, and set up I2C and I2S for
TAS2563. Also pass the corresponding GPIO(s) to the payload.
TEST=build pass and driver init ok
BUG=b:357969183
Change-Id: I10cba7964d3847f2a74341b3130ff1e7bfd8d37a
Signed-off-by: Darren Ye <darren.ye@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85360
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
HW TX tracking works by writing a pattern to the designated DRAM buffer
and then reading it back automatically to calculate the appropriate TX
time delay. To avoid writing the pattern to system-used memory, we need
to permanently reserve last 64KB memory on each rank for the HW TX
tracking feature.
BUG=b:317009620
TEST=Reserve memory ok
Firmware shows the following log with 12GB DDR board:
00000001ffff0000-00000001ffffffff: RESERVED
000000037fff0000-000000037fffffff: RESERVED
Change-Id: I042a74c7fbdc0d3dc19dd6bfd2bf021fe1c2b5fc
Signed-off-by: Crystal Guo <crystal.guo@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85124
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Since commit e633d370 (soc/intel/cometlake: Enable early caching of
RAMTOP region), cmos.layout for Cannon Lake boards must have a ramtop
entry, add it.
Change-Id: I2bf71f2dd79f2e1e2e13f62a3e08103336bbad61
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77670
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the DEV_PTR macro to resolve devicetree aliases instead of using the
autogenerated reference names from sconfig directly.
TEST=Timeless build did not change
Change-Id: I4ff06bb3a8256d5fe215cab659f33ec404264e21
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85093
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Fix the syntax [1] for the footnote about the onboard memory
configuration so that it renders properly in the generated html.
This also fixes a "Unknown target name" error when building with
newer versions of Sphinx (tested with 8.1.3).
[1] https://myst-parser.readthedocs.io/en/latest/syntax/typography.html#footnotes
Change-Id: I07a85b854a181794f82d8e6a739063d66378d2c7
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85412
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Add Micron memory part H58G56CK8BX146 to LP5 global list.
And Regenerate the SPD files for the SoC. The specification
is attached in issue tracker.
BUG=b:367841051
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: I2a003aad32bca9ae5438973ecf0d7872481fee20
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
