This commit introduces changes to the ACPI implementation for the
PTLRVP mainboard by adding power meter support. It defines how the
PAC194x series devices are connected to the I2C controller and details
their configuration. Each device under scope \_SB.PCI0.I2C3 is given
specific methods to indicate its status, resource settings, and device
specific configurations via _DSM. This includes functionality to return
monitored power rail names, resistor values, EMI configurations, sample
frequencies, and Vbus multiplication factors. These changes enhance
the power management capabilities of the mainboard, allowing precise
monitoring and control over various power rails.
BUG=none
TEST=Verify power meter ACPI changes in DSDT.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I6e5d38500cac46187283481ef6f84215b14e927b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
As a result of hardware BOM design, U51 (power gate for touchscreen)
would be required to remove on non-touch SKU. The change will cause
the I2C1 touchscreen devices probe ERROR of non-touch SKU since no
power for I2C bus pull-high resistors.The ERROR is waiting I2C stop
condition time out then bootperf test will get fail.
The CL apply fw_config field 19 - PANEL_PWR_SEQ_CTRL for I2C1:
0...disable (non-touch sku)
1...enable (touch sku)
Turn off I2C1 for non-touch sku, and keep I2C1 is on for touch sku.
It will avoid the touchscreen probing error on I2c1.
BUG=b:447513390
TEST=Check boot to kernel time is 1,376 sec under spec and without
I2C probe error in ap log of non-touch sku.
Check touchscreen device works well of touch sku.
Change-Id: I72a68177a90cea88fe283d8499b8378c64206fa2
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
The help description for `CONFIG_BMP_LOGO` in `src/lib/Kconfig` is
updated to be more generic.
Change-Id: Ic95aabe3fa3178ed5a8e4a2105364e8fb397d85f
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Update Kconfig.name with device/product names where available. Names
were parsed from a ChromeOS Recovery image config file, and matched
to the appropriate board using a script generated by Cursor AI.
Output was spot checked for correctness and compared to other sources.
Development devices were dropped from the results.
Change-Id: I5ac1c153606b7d1f93ea5c72e5ff727bb1f38683
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Unlike already implemented Keyboard Controller Style (KCS) interface
Block Transfer interface is not byte-oriented and implies that device is
capable of buffering a command before processing it. Another difference
is that polling can be replaced with interrupts, though this isn't used
by this implementation.
More details can be found in "Intelligent Platform Management Interface
Specification", v2.0, Rev. 1.1:
https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/ipmi-intelligent-platform-mgt-interface-spec-2nd-gen-v2-0-spec-update.pdf
This was initially tested on Talos II (OpenPower platform) by Raptor
Computing Systems. Later versions were tested using QEMU and ipmi_sim
from OpenIPMI project as well as QEMU's builtin BMC simulator.
Change-Id: Idb67972d1c38bbae04c7b4de3405350c229a05b9
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67057
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the DPTF parameters as provided by thermal team.
1. Adjust the PSV threshold value of the Passive Policy.
BUG=b:449890912
BRANCH=firmware-trulo-15217.771.B
TEST=build test firmware and verified by thermal team
Change-Id: I8be7da7550994f6a408e2c5bbc6ae4d31fa22ada
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89564
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The hardware is mostly identical to the well supported Thinkpad T480
aside from some swapped PCIe clock lines. Consequently, coreboot will
boot to the OS in combination with a properly deguarded Intel ME.
The VBT was obtained from the latest stock BIOS (1.43, N27ET57W) with
intelvbttool. GPIO assignments have been cross-checked against publicly
available schematics (Tachi-2).
The patches have been validated on a Thinkpad T580 P/N 20L9-001NUS. With
SeaBIOS rel-1.17.0-4 as payload, the system boots into Linux (debian 13)
and Windows 10 22H2 with the hardware working as expected.
Change-Id: Iaa8368aeda11560bc0c1c77e7611ed9879d038da
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89499
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Issue=ACP is not running in S3 because the XTAL FCH CLK is turned off.
ACP needs to be running in S3 for one of our customers who needs audio
playback to work in S3.
Fix=Introduce a config option to control this setting.
TEST=Tested this in ACPI S3 state,by connecting an external CODEC and
transmitting a known pattern to the ACP via the I2S TDM controller RX
lines and ensuring that the sound is output to the speaker connected
to the CODEC via the TDM TX line.
Change-Id: Ie9c0e96f87050b542a1ddf3f59d6b67064ac8faf
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Both of these boards have 20Gbps TBT2 ports, capable of accessing
PCIe labels from the PCH. Therefore, select
SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES.
Change-Id: I4528f2748d1fa3988296f695dac045de536c43df
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The second port was set to 07.0, which is the first port. Correct
this.
Change-Id: I8d1a046ea863beb921c103cb2aa82b09d75f2be7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89595
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set pads that are not used to PAD_NC
Change-Id: I1a50bc8eab9d086b71cc33f56789bdd10f133864
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
It seems that FSP was fixing up the TBT0 TXD and RXD GPIOs;
add the missing GPIO configuration and group them.
Change-Id: I22af542fe008395a47c64396f481442ff3bcc9a7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89584
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Emply the standard Star Labs format for the config straps; this is
a non-functional change - just easier to read.
Change-Id: I04c7a8046c21577154593996866448fc4c05d03b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Set pads that are not used to PAD_NC.
Change-Id: I3bf005b743fdcaf75c456c59354e7440ec0faefb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89581
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Apply the standard format for configuring the config straps. The
configuration of the straps isn't changed, just written more clearly.
Change-Id: I2cf130fbf7572a4014e97c14885951e5f604cfa8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89578
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Non-functional change that makes it easier to see what is actually
configured.
Change-Id: I2ffb11ef73a0b2c9e5236b2edb9ec187a045374c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89582
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add framebuffer region to reserve 24MB for the boot logo feature.
BUG=b:319511268
TEST=The logo is shown in the ramstage.
Change-Id: I183651f7bd28de5551a15bd335bc2eed5f0804eb
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The RW_A and RW_B firmware sections are increased by 256KB, from 1500K
to 1756K, to support larger firmware images. With bootsplash enabled,
the remaining space in these sections is approximately 15KB, which is
insufficient to hold the bootsplash assets. This increase provides the
necessary space. Additionally, with more features anticipated from the
payload (depthcharge), this extra space serves as a reserve to prevent
future build failures due to insufficient space.
The RW_LEGACY section is also adjusted to fill the remaining space.
WARNING: Please do NOT cherry-pick to rauru firmware branch.
BUG=b:450510630,b:319511268
TEST=emerge-rauru coreboot chromeos-bootimage (with BMP_LOGO enabled)
Change-Id: I70aaa9e7011b7f2376b7bc28caac27c0a86aa20a
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This change introduces support for displaying a bootsplash logo during
boot on Mediatek platforms.
A new `display_logo` function is added to render a logo from the CBFS
into the framebuffer. This function is called from `mtk_display_init` if
`BMP_LOGO` is enabled in the board's Kconfig.
Additionally, this change refactors the backlight configuration logic
into a new `panel_configure_backlight` helper function for better
clarity.
BUG=b:319511268
TEST=Verified on Hylia that the bootsplash logo is displayed correctly
during ramstage. Boot time increased by 562ms due to display
initialization.
Change-Id: Ibcfaa7d309eb4a0b14244b98c78a0dc32e6836e5
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89543
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To save memory, only allocate and configure the framebuffer when display
output is required during boot.
This is achieved by:
1. Making the `framebuffer` memory region optional.
2. Guarding the framebuffer's uncached MMU configuration with a
`display_init_required()` check.
This ensures the framebuffer is prepared only when needed, saving
memory on boot paths that do not require display.
BUG=b:319511268
BRANCH=none
TEST=emerge-rauru coreboot
Change-Id: I3808031160e421de7c21f585f4b79d42bfddccc4
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89541
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reserve DDR region for HYP, QTEE SMMU buffers, Gunyah and ACDB. The
carveout is located at: 0xFF800000 - ((n*5.5)+1+32+3), where n is
the DRAM size. This region is protected by QTEE and must remain
reserved to prevent access by other components.
TEST=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified carveout region reservation via depthcharge serial log.
Prior to reservation, the memory wipeout range was [0x000000f61f7920,
0x000000ff800000). After reserving the carveout, the range is reduced
to [0x000000f61f7920, 0x000000f7c00000).
```
Wipe memory regions:
[0x00000080000000, 0x00000080a00000)
[0x000000815a0000, 0x00000081a00000)
[0x00000081cf4000, 0x00000081e00000)
[0x00000082800000, 0x00000085380000)
[0x00000085f80000, 0x000000866c0000)
[0x00000091380000, 0x000000c72c4000)
[0x000000c7800000, 0x000000d8000000)
[0x000000d9600000, 0x000000f1000000)
[0x000000f61f7920, 0x000000f7c00000)
[0x00000880000000, 0x00000c00000000)
```
Change-Id: I511452054dcf10f8a2254eafb2f127c05a3249e5
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89552
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Complies with the Multi-Processor (MP) service as defined by the
EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo() in the Platform
Initialization Specification 1.7. If bit 24 (CPU_V2_EXTENDED_TOPOLOGY)
is set in ProcessorId, GetProcessorInfo() must populate the
EFI_CPU_PHYSICAL_LOCATION2 data structure.
TEST=FSP using PI 1.7 GetProcessorInfo() is able to retrieve the
information instead of receiving an EFI_NOT_FOUND error.
Change-Id: If4d473901c8de02b3d6cef44f5481a1864f14d65
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89462
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Commit 743e3a07f5 ("mb/google/brya/var/nissa: Remove duplicate ACPI
device GFX0") removed the GMA default panel and replaced it with the
generic gfx device, but left out the device type field, which resulted
in changes to the _DOD and _ADR methods for the GFX0 ACPI device.
This change caused Windows to ignore the ACPI brightness controls,
leaving the display fixed at full brightness. Add the missing device
type entry to restore the brightness control functionality.
before (incorrect):
_DOD: 0x80010000
_ADR: Zero
after (correct):
_DOD: 0x80010400
_ADR: 0x00000400
TEST=build/boot Win11, Linux on craaskvin, verify brightness controls
functional under both OSes.
Change-Id: Ia0cfcec14963605ce874c6c7ed6b26c725cf74f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
SATA_DEVSLP1B and PEDET were simply missed, so configure them
Change-Id: Iface1f19c5a93f5a911861fbad7fa4b3f808bfef
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89577
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, it just puts them into a the same
format as the other Star Labs boards.
Change-Id: I849d0b50490eec6b6c58bd0fd29f57e434ba95c4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89575
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The wrong definition was used, so fix it.
Change-Id: I7ebbf0dcba4117ddeaa496b6faa83561d82c621d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
When Thunderbolt was disabled in the option table, only
VtdBaseAddress[3] was zero'd, when it should be
VtdBaseAddress[4] as well.
Change-Id: I63e3cefcb74c2ef31b5b0180d13a4720a6d7d0c2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89553
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a non-functional change, as the settings remain the same, and
it's only done as a pre-caution as FSP has been funny with VBT versions
before.
Change-Id: Ie7978e76286b3e2ff21fd0a28bfe51bdfd32f381
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89547
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add BT _PRR related methods to mitigate BT lost issue.
Refer to Intel TA#837249, toggling BTEN, BT_IF_SELECT, and
BT_RESET_GPIO to recovery BT device when BT became a low-speed usb
device.
BUG=b:451095940
TEST=Run reboot stress and check kernel log, BT could be recovery.
usb 3-10: new full-speed USB device number 4 using xhci_hcd
usb 3-10: New USB device found, idVendor=8087, idProduct=0033,
bcdDevice= 0.00
usb 3-10: New USB device strings: Mfr=0, Product=0, SerialNumber=0
usb 3-10: using ACPI '\_SB.PCI0.XHCI.RHUB.HS10' for 'reset' GPIO lookup
usb 3-10: USB disconnect, device number 4
usb 3-10: new low-speed USB device number 5 using xhci_hcd
usb 3-10: device descriptor read/64, error -71
usb 3-10: device descriptor read/64, error -71
usb 3-10: new low-speed USB device number 6 using xhci_hcd
usb 3-10: device descriptor read/64, error -71
usb 3-10: device descriptor read/64, error -71
usb 3-10: new full-speed USB device number 7 using xhci_hcd
usb 3-10: New USB device found, idVendor=8087, idProduct=0033,
bcdDevice= 0.00
Change-Id: I0d485a9102676624da28d5d681ea4510444e17bd
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89384
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit introduces support for configuring power state current
thresholds (PS1, PS2, PS3) for each Voltage Regulator (VR) domain in the
Panther Lake SoC.
The thresholds allow platform integrators to specify current thresholds
(in 1/4 A increments, 0-128 A) for each VR domain and power state. A
value of 0 indicates AUTO (use default).
Change-Id: If4d473901c8de02b3d6cef44f5481a1864f14d63
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
This commit adds the capability to configure TDC mode and time window
for each Voltage Regulator (VR) domain, providing better control over
thermal constraints and power consumption.
The TDC mode specifies the method (iPL2 or Irms) used for thermal
management, while the time window determines the duration for current
averaging.
Change-Id: I2e11855c4f0533d826a25efead02ddcff9ab1f62
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Add configuration for Maximum Integrated Circuit Current (ICC) for
various SKUs and VR domains. The ICC values, defined in 1/4A increments,
specify the maximum allowable current for a given SKU and VR domain
configuration. This update enhances power management by allowing
tailored ICC settings.
Change-Id: I2c4712521da7b89cd4b2a6c499e11245b8eeb719
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88044
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces configuration options for P-core and E-core
hysteresis time windows to support acoustic noise mitigation on Intel
Panther Lake (PTL) System on Chips (SoCs).
Change-Id: Ic3bceda06adf4e0a81b0503e5fb65895bfad2c12
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89333
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
The changes focus on offering power state current thresholds, Thermal
Design Current (TDC) mode settings, and P-core and E-core hysteresis time
windows to support acoustic noise mitigation.
The Ps1Threshold, Ps2Threshold, and Ps3Threshold new fields configure
current thresholds for different power states. This allows for
fine-tuned power management by specifying current thresholds in 1/4 A
increments. These configurations can help optimize performance based on
specific current requirements for different components like IA, GT, and
SA.
The TdcMode parameter configures TDC mode based on the IRMS supported
bit from Mailbox, offering the option between iPL2 and Irms modes.
BUG=b:449662274
Change-Id: I949dd6a5c6bf575415ee62dcd0d0eda369ef29fc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89330
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ReportingPchPmDisableEnergyReport has been 0 by default in all
FSP versions up until Meteor Lake. Set this to unify the
configuration between boards.
No applicable tests.
Change-Id: If9cdbb466bf8e4efc7a1577b0a1fec6270550d05
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89527
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only PmcLpmS0ixSubStateEnableMask is currently configured, and
PmcPchLpmS0ixSubStateEnableMask is left with the default value.
These should be the same.
Change-Id: I71bebec251c5c336407c2c173af29ddbfde0691b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These do not need to be configured, as they're configured
automatically on reset.
Change-Id: I26c9a42fa44b55208583859895f9a39016e76eac
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89523
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces necessary changes to correctly initialize the
Qualcomm X1p42100 USB4/DP PHY based on the USB Type-C CC polarity
detection.
When a Type-C cable is connected, the CC lines determine the
connector orientation (polarity). The USB PHY lanes must be swapped
accordingly to ensure the SuperSpeed signals are routed correctly.
Key changes:
- Adds 'get_usb_typec_polarity()' to read the CC polarity state from
the PMIC (SMB1/SMB2) via the 'SCHG_TYPE_C_MISC_STATUS' register.
- Extends 'qmp_usb4_dp_phy_ss_init()' to accept a 'polarity_inverse'
boolean.
- Uses the polarity state to set the 'SW_PORTSELECT' register in the
USB4/DP common configuration, effectively swapping the lanes when
needed.
- Calls the updated PHY initialization function with the appropriate
polarity for both primary (SS0) and secondary (SS1) USB instances.
This ensures robust USB functionality regardless of the cable insertion
orientation.
BUG=b:448107633
TEST=Verify USB-C works in both polarities on Google/Quenbi.
Without this CL -
USB3 key doesn't work in inverted polarity.
With this CL -
USB3 key works in both polarities.
Change-Id: I1855a12e32a76032d4c1b57770143c152b806008
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Enhancements have been made to the Intel touch driver, including support
for Google touchscreen devices, ELAN9006 and ELAN6918. The update
also includes device-specific configuration changes for both I2C and SPI
interfaces.
Key improvements include:
- Google Touchscreen support integration for ELAN9006 (SPI) and ELAN6918
(I2C).
- Specification of recommended connection speeds for supported devices.
- Removal of an unnecessary 100ms delay in the SPI _RST method.
- Addition of a function to map the System on Chip's (SoC) I2C speed
frequency.
- Improved device-specific connection speed settings for both I2C and
SPI interfaces.
These changes aim to improve the driver’s compatibility and efficiency
when interacting with the newly supported devices.
BUG=none
TEST=Test the updated driver on devices using ELAN9006 and ELAN6918 to
verify improved responsiveness and correct device initialization.
Confirm that connection speeds are set as recommended and check the
absence of the previously unnecessary delay in SPI operations from the
SSDT.
Change-Id: Ie35de90ece44101aea008d13d19e12873cdc09bf
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit makes the tile and die ID CPU topology parameters
information available to support the implementation of
EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo() in accordance with the
Platform Initialization Specification 1.7.
TEST=Instrumentation shows that the tile_id and die_id apic_path fields
are properly populated.
Change-Id: If4d473901c8de02b3d6cef44f5481a1864f14d64
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89461
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When configuring the touch_thc_i2c controlled touchpad and touchscreen
for the first time, referring to the fatcat code. The touchpad and
touchscreen could not be successfully bringup, since the touchpad and
touchscreen configured in the code are opposite to those in the fatcat
schematic diagram. According to the circuit schematic
NB7835CAA_SCH_MB_V1_A.pdf, modify the GPIO configuration and devicetree.
1. Configure GPIO as THC-I2C function.
2. Modify devicetree
touchpad ==> THC0
touchpanel ==> THC1
BUG=b:448030832 b:445817408
TEST=emerge-fatcat coerboot chromeos-bootimage
flash to DUT, touchpad and touchpanel can be found by `getevent`
Change-Id: I6826145f58d437e03683a4459ded3b7657cf616a
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89383
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the PinMux is configured correctly, these no longer
need to be set, as they're configured automatically on reset.
Change-Id: I03c6431f6ce7118444ef3672de32c5afa2e36441
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
When the board uses OpenSIL, the OpenSIL include paths already include
the $(top). Vboot patches the paths so that all of them include $(top)
at the beginning. This however would result in the include paths from
OpenSIL to include $(top) twice. Filter the paths that already contain
the $(top) and strip the prefix. Then add the $(top) prefix again to
all include paths to fix the problem.
TEST=Build vboot lib selected by enabled measured boot on Gigabyte MZ33-AR1.
Change-Id: Id67ea760f7b1ee2212f19a875c905771cdecdfa5
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89114
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
