mb/lenovo/sklkbl_thinkpad: Add Lenovo Thinkpad T580 as a variant
The hardware is mostly identical to the well supported Thinkpad T480 aside from some swapped PCIe clock lines. Consequently, coreboot will boot to the OS in combination with a properly deguarded Intel ME. The VBT was obtained from the latest stock BIOS (1.43, N27ET57W) with intelvbttool. GPIO assignments have been cross-checked against publicly available schematics (Tachi-2). The patches have been validated on a Thinkpad T580 P/N 20L9-001NUS. With SeaBIOS rel-1.17.0-4 as payload, the system boots into Linux (debian 13) and Windows 10 22H2 with the hardware working as expected. Change-Id: Iaa8368aeda11560bc0c1c77e7611ed9879d038da Signed-off-by: Johann C. Rode <jcrode@gmx.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89499 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Johann C. Rode
Matt DeVillier
parent
d23eaa356f
commit
3747b47df1
9 changed files with 455 additions and 1 deletions
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@ -35,6 +35,13 @@ config BOARD_LENOVO_T480S
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select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
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select VARIANT_HAS_DGPU
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config BOARD_LENOVO_T580
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bool
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select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
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select MEC1653_HAS_DEBUG_UNLOCK
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select VARIANT_HAS_DGPU
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if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
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config MAINBOARD_DIR
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@ -43,6 +50,7 @@ config MAINBOARD_DIR
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config VARIANT_DIR
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default "t480" if BOARD_LENOVO_T480
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default "t480s" if BOARD_LENOVO_T480S
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default "t580" if BOARD_LENOVO_T580
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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@ -50,6 +58,7 @@ config OVERRIDE_DEVICETREE
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config MAINBOARD_PART_NUMBER
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default "T480" if BOARD_LENOVO_T480
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default "T480s" if BOARD_LENOVO_T480S
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default "T580" if BOARD_LENOVO_T580
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config CBFS_SIZE
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default 0x900000
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@ -85,7 +94,7 @@ config THINKPADEC_HKEY_EISAID
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default "LEN0268"
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config MEC1653_DEBUG_UNLOCK_KEY
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default "7a41b149fe2101cf" if BOARD_LENOVO_T480
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default "7a41b149fe2101cf" if BOARD_LENOVO_T480 || BOARD_LENOVO_T580
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config VARIANT_HAS_DGPU
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bool
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@ -5,3 +5,6 @@ config BOARD_LENOVO_T480
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config BOARD_LENOVO_T480S
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bool "ThinkPad T480s"
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config BOARD_LENOVO_T580
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bool "ThinkPad T580"
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BIN
src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/data.vbt
Normal file
BIN
src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/data.vbt
Normal file
Binary file not shown.
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@ -0,0 +1,19 @@
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-- SPDX-License-Identifier: GPL-2.0-or-later
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with HW.GFX.GMA;
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with HW.GFX.GMA.Display_Probing;
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use HW.GFX.GMA;
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use HW.GFX.GMA.Display_Probing;
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private package GMA.Mainboard is
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ports : constant Port_List :=
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(eDP,
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DP1,
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DP2,
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HDMI1,
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HDMI2,
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others => Disabled);
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end GMA.Mainboard;
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203
src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c
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203
src/mainboard/lenovo/sklkbl_thinkpad/variants/t580/gpio.c
Normal file
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@ -0,0 +1,203 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/gpio.h>
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#include "../../variant.h"
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/* FIXME: There are multiple GPIOs here that should be locked to prevent "TPM GPIO fail" style
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* attacks. Unfortunately SKL/KBL GPIO locking *does not* work currently. */
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Community 0 ------- */
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/* ------- GPIO Group GPP_A ------- */
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PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */
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PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */
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PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */
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PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */
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PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */
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PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */
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PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */
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PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */
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PAD_CFG_NF(GPP_A9, NATIVE, DEEP, NF1), /* LPCCLK_EC_24M */
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PAD_CFG_NF(GPP_A10, NATIVE, DEEP, NF1), /* LPCCLK_DEBUG_24M */
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PAD_NC(GPP_A11, NONE),
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PAD_NC(GPP_A12, NONE),
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PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1), /* -SUSWARN */
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PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1), /* -SUS_STAT */
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PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1), /* -SUSWARN */
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PAD_NC(GPP_A16, NONE),
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PAD_NC(GPP_A17, NONE),
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PAD_NC(GPP_A18, NONE),
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PAD_NC(GPP_A19, NONE),
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PAD_NC(GPP_A20, NONE),
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PAD_NC(GPP_A21, NONE),
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PAD_NC(GPP_A22, NONE),
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PAD_NC(GPP_A23, NONE),
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/* ------- GPIO Group GPP_B ------- */
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PAD_NC(GPP_B0, NONE),
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PAD_NC(GPP_B1, NONE),
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PAD_NC(GPP_B2, NONE),
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PAD_NC(GPP_B3, NONE),
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PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), /* -TBT_PLUG_EVENT */
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 */
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE4 */
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 */
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE10 */
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PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* -CLKREQ_PCIE8 */
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PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE6 */
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PAD_NC(GPP_B11, NONE),
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */
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PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1), /* PCH_SPKR */
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PAD_CFG_GPO(GPP_B15, 1, DEEP), /* NFC_DLREQ */
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PAD_NC(GPP_B16, NONE),
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PAD_NC(GPP_B17, NONE),
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PAD_NC(GPP_B18, NONE),
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PAD_NC(GPP_B19, NONE),
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PAD_NC(GPP_B20, NONE),
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PAD_NC(GPP_B21, NONE),
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PAD_NC(GPP_B22, NONE),
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PAD_NC(GPP_B23, NONE),
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/* ------- GPIO Community 1 ------- */
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/* ------- GPIO Group GPP_C ------- */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */
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PAD_NC(GPP_C2, NONE),
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */
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PAD_NC(GPP_C5, NONE),
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PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */
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PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */
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PAD_NC(GPP_C8, NONE),
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PAD_NC(GPP_C9, NONE),
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PAD_NC(GPP_C10, NONE),
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PAD_NC(GPP_C11, NONE),
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PAD_NC(GPP_C12, NONE),
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PAD_NC(GPP_C13, NONE),
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PAD_NC(GPP_C14, NONE),
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PAD_NC(GPP_C15, NONE),
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */
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PAD_NC(GPP_C18, NONE),
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PAD_NC(GPP_C19, NONE),
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PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */
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PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */
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PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */
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PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */
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/* ------- GPIO Group GPP_D ------- */
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PAD_NC(GPP_D0, NONE),
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PAD_NC(GPP_D1, NONE),
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PAD_NC(GPP_D2, NONE),
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PAD_NC(GPP_D3, NONE),
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PAD_NC(GPP_D4, NONE),
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PAD_NC(GPP_D5, NONE),
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PAD_NC(GPP_D6, NONE),
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PAD_NC(GPP_D7, NONE),
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PAD_NC(GPP_D8, NONE),
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PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), /* -DISCRETE_PRESENCE */
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PAD_NC(GPP_D10, NONE),
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PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID0 */
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PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID1 */
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PAD_NC(GPP_D13, NONE),
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PAD_NC(GPP_D14, NONE),
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PAD_NC(GPP_D15, NONE),
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PAD_NC(GPP_D16, NONE),
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PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY1 */
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PAD_NC(GPP_D18, NONE),
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PAD_NC(GPP_D19, NONE),
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PAD_NC(GPP_D20, NONE),
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PAD_NC(GPP_D21, NONE),
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PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */
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PAD_NC(GPP_D23, NONE),
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/* ------- GPIO Group GPP_E ------- */
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PAD_NC(GPP_E0, NONE),
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PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* -WWAN_SATA_DTCT (always HIGH) */
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PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* -PE_DTCT */
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PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), /* -TBT_PLUG_EVENT */
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PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */
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PAD_NC(GPP_E5, NONE),
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PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), /* SATA2_DEVSLP */
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PAD_NC(GPP_E7, NONE),
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PAD_NC(GPP_E8, NONE),
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PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 (AON port) */
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PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 (regular port) */
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PAD_NC(GPP_E11, NONE),
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PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */
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PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */
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PAD_NC(GPP_E15, NONE),
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PAD_NC(GPP_E16, NONE),
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PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */
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PAD_NC(GPP_E18, NONE),
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PAD_NC(GPP_E19, NONE),
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PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */
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PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */
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PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST), /* -GPU_RST */
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PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST), /* 1R8VIDEO_AON_ON */
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/* ------- GPIO Community 2 ------- */
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/* -------- GPIO Group GPD -------- */
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PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */
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PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */
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PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */
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PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */
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PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */
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PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */
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PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */
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PAD_NC(GPD7, NONE),
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PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */
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PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */
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PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */
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PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */
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/* ------- GPIO Community 3 ------- */
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/* ------- GPIO Group GPP_F ------- */
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PAD_NC(GPP_F0, NONE),
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PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GC6_FB_EN */
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PAD_CFG_GPO(GPP_F2, 1, DEEP), /* -GPU_EVENT */
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PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, ACPI), /* DGFX_PWRGD */
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PAD_CFG_GPO(GPP_F4, 1, DEEP), /* -WWAN_RESET */
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PAD_NC(GPP_F5, NONE),
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PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI), /* -MIC_HW_EN (R961 to GND) */
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PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI), /* -INT_MIC_DTCT */
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PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG0 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG1 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG2 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG3 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI), /* PLANARID0 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI), /* PLANARID1 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI), /* PLANARID2 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI), /* PLANARID3 */
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PAD_NC(GPP_F16, NONE),
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PAD_NC(GPP_F17, NONE),
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PAD_NC(GPP_F18, NONE),
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PAD_NC(GPP_F19, NONE),
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PAD_NC(GPP_F20, NONE),
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PAD_NC(GPP_F21, NONE),
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PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI), /* -INTRUDER_PCH */
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PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI), /* -SC_DTCT */
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/* ------- GPIO Group GPP_G ------- */
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PAD_NC(GPP_G0, NONE),
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PAD_NC(GPP_G1, NONE),
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PAD_NC(GPP_G2, NONE),
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PAD_NC(GPP_G3, NONE),
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PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */
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PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */
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PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */
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PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */
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};
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void variant_config_gpios(void)
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{
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gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
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}
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@ -0,0 +1,89 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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0x10ec0257, // Vendor/Device ID: Realtek ALC257
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0x17aa225a, // Subsystem ID
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11,
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AZALIA_SUBVENDOR(0, 0x17aa225a),
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AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
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AZALIA_INTEGRATED,
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AZALIA_INTERNAL,
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AZALIA_MIC_IN,
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AZALIA_OTHER_DIGITAL,
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AZALIA_COLOR_UNKNOWN,
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AZALIA_NO_JACK_PRESENCE_DETECT,
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2, 0
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)),
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AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device
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AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
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AZALIA_INTEGRATED,
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AZALIA_INTERNAL,
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AZALIA_SPEAKER,
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AZALIA_OTHER_ANALOG,
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AZALIA_COLOR_UNKNOWN,
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AZALIA_NO_JACK_PRESENCE_DETECT,
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1, 0
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)),
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AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
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AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
|
||||
AZALIA_JACK,
|
||||
AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
|
||||
AZALIA_MIC_IN,
|
||||
AZALIA_STEREO_MONO_1_8,
|
||||
AZALIA_BLACK,
|
||||
AZALIA_JACK_PRESENCE_DETECT,
|
||||
3, 0
|
||||
)),
|
||||
AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device
|
||||
AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
|
||||
AZALIA_JACK,
|
||||
AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
|
||||
AZALIA_HP_OUT,
|
||||
AZALIA_STEREO_MONO_1_8,
|
||||
AZALIA_BLACK,
|
||||
AZALIA_JACK_PRESENCE_DETECT,
|
||||
1, 15
|
||||
)),
|
||||
|
||||
0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI
|
||||
0x80860101, // Subsystem ID
|
||||
4,
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
|
||||
AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC(
|
||||
AZALIA_JACK,
|
||||
AZALIA_DIGITAL_DISPLAY,
|
||||
AZALIA_DIGITAL_OTHER_OUT,
|
||||
AZALIA_OTHER_DIGITAL,
|
||||
AZALIA_COLOR_UNKNOWN,
|
||||
AZALIA_JACK_PRESENCE_DETECT,
|
||||
1, 0
|
||||
)),
|
||||
AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
|
||||
AZALIA_JACK,
|
||||
AZALIA_DIGITAL_DISPLAY,
|
||||
AZALIA_DIGITAL_OTHER_OUT,
|
||||
AZALIA_OTHER_DIGITAL,
|
||||
AZALIA_COLOR_UNKNOWN,
|
||||
AZALIA_JACK_PRESENCE_DETECT,
|
||||
1, 0
|
||||
)),
|
||||
AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
|
||||
AZALIA_JACK,
|
||||
AZALIA_DIGITAL_DISPLAY,
|
||||
AZALIA_DIGITAL_OTHER_OUT,
|
||||
AZALIA_OTHER_DIGITAL,
|
||||
AZALIA_COLOR_UNKNOWN,
|
||||
AZALIA_JACK_PRESENCE_DETECT,
|
||||
1, 0
|
||||
)),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _VARIANT_DGPU_H_
|
||||
#define _VARIANT_DGPU_H_
|
||||
|
||||
#define GPIO_GPU_RST GPP_E22 // active low
|
||||
#define GPIO_1R8VIDEO_AON_ON GPP_E23
|
||||
|
||||
#define GPIO_DGFX_PWRGD GPP_F3
|
||||
|
||||
#define GPIO_DISCRETE_PRESENCE GPP_D9 // active low
|
||||
#define GPIO_DGFX_VRAM_ID0 GPP_D11
|
||||
#define GPIO_DGFX_VRAM_ID1 GPP_D12
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/romstage.h>
|
||||
#include <spd_bin.h>
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
|
||||
mem_cfg->DqPinsInterleaved = false; /* DDR_DQ in interleave mode */
|
||||
mem_cfg->CaVrefConfig = 2; /* VREF_CA to CH_A and VREF_DQ_B to CH_B */
|
||||
mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
|
||||
|
||||
/* Get SPD for memory slots */
|
||||
struct spd_block blk = { .addr_map = { 0x50, 0x51, } };
|
||||
get_spd_smbus(&blk);
|
||||
dump_spd_info(&blk);
|
||||
|
||||
mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
|
||||
mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
|
||||
}
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/skylake
|
||||
device domain 0 on
|
||||
device ref south_xhci on
|
||||
register "usb2_ports" = "{
|
||||
[0] = USB2_PORT_MID(OC1), // USB-A
|
||||
[1] = USB2_PORT_MID(OC0), // USB-A (always on)
|
||||
[2] = USB2_PORT_MID(OC_SKIP), // JSC-1 (smartcard slot)
|
||||
[3] = USB2_PORT_MID(OC_SKIP), // USB-C (charging port)
|
||||
[4] = USB2_PORT_MID(OC_SKIP), // JCAM1 (IR camera)
|
||||
[5] = USB2_PORT_MID(OC_SKIP), // JWWAN1 (M.2 WWAN USB)
|
||||
[6] = USB2_PORT_MID(OC_SKIP), // JWLAN1 (M.2 WLAN USB)
|
||||
[7] = USB2_PORT_MID(OC_SKIP), // JCAM1 (webcam)
|
||||
[8] = USB2_PORT_MID(OC_SKIP), // JFPR1 (fingerprint reader)
|
||||
[9] = USB2_PORT_MID(OC_SKIP), // JLCD1 (touch panel)
|
||||
}"
|
||||
register "usb3_ports" = "{
|
||||
[0] = USB3_PORT_DEFAULT(OC1), // USB-A
|
||||
[1] = USB3_PORT_DEFAULT(OC0), // USB-A (always on)
|
||||
[2] = USB3_PORT_DEFAULT(OC_SKIP), // RTS5344S (SD card reader)
|
||||
[3] = USB3_PORT_DEFAULT(OC_SKIP), // USB-C (charging port)
|
||||
}"
|
||||
end
|
||||
|
||||
# PCIe controller 1 - 1x4
|
||||
# PCIE 1-4 - RP1 - dGPU - CLKOUT0 - CLKREQ0
|
||||
#
|
||||
# PCIe controller 2 - 2x1+1x2 (lane reversal)
|
||||
# PCIE 5 - GBE - GBE - CLKOUT1 - CLKREQ1 (clobbers RP8)
|
||||
# PCIE 6 - RP7 - WLAN - CLKOUT2 - CLKREQ2
|
||||
# PCIE 7-8 - RP5 - WWAN - CLKOUT3 - CLKREQ3
|
||||
#
|
||||
# PCIe controller 3 - 2x2
|
||||
# PCIE 9-10 - RP9 - TB3 - CLKOUT4 - CLKREQ4
|
||||
# PCIE 11-12 - RP11 - SSD - CLKOUT5 - CLKREQ5
|
||||
|
||||
# dGPU - x4
|
||||
device ref pcie_rp1 on
|
||||
register "PcieRpClkReqSupport[0]" = "true"
|
||||
register "PcieRpClkReqNumber[0]" = "0"
|
||||
register "PcieRpClkSrcNumber[0]" = "0"
|
||||
register "PcieRpAdvancedErrorReporting[0]" = "true"
|
||||
register "PcieRpLtrEnable[0]" = "true"
|
||||
device generic 0 alias dgpu on end
|
||||
end
|
||||
|
||||
# Ethernet (clobbers RP8)
|
||||
device ref gbe on
|
||||
register "LanClkReqSupported" = "true"
|
||||
register "LanClkReqNumber" = "1"
|
||||
register "EnableLanLtr" = "true"
|
||||
register "EnableLanK1Off" = "true"
|
||||
end
|
||||
|
||||
# M.2 WLAN - x1
|
||||
device ref pcie_rp7 on
|
||||
register "PcieRpClkReqSupport[6]" = "true"
|
||||
register "PcieRpClkReqNumber[6]" = "2"
|
||||
register "PcieRpClkSrcNumber[6]" = "2"
|
||||
register "PcieRpAdvancedErrorReporting[6]" = "true"
|
||||
register "PcieRpLtrEnable[6]" = "true"
|
||||
smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
|
||||
end
|
||||
|
||||
# M.2 WWAN - x2
|
||||
device ref pcie_rp5 on
|
||||
register "PcieRpClkReqSupport[4]" = "true"
|
||||
register "PcieRpClkReqNumber[4]" = "5"
|
||||
register "PcieRpClkSrcNumber[4]" = "5"
|
||||
register "PcieRpAdvancedErrorReporting[4]" = "true"
|
||||
register "PcieRpLtrEnable[4]" = "true"
|
||||
smbios_slot_desc "SlotTypeM2Socket2" "SlotLengthOther" "M.2/B 3042/2242" "SlotDataBusWidth2X"
|
||||
end
|
||||
|
||||
# TB3 (Alpine Ridge LP) - x2
|
||||
device ref pcie_rp9 on
|
||||
register "PcieRpClkReqSupport[8]" = "true"
|
||||
register "PcieRpClkReqNumber[8]" = "4"
|
||||
register "PcieRpClkSrcNumber[8]" = "4"
|
||||
register "PcieRpAdvancedErrorReporting[8]" = "true"
|
||||
register "PcieRpLtrEnable[8]" = "true"
|
||||
register "PcieRpHotPlug[8]" = "true"
|
||||
end
|
||||
|
||||
# M.2 2280 caddy - x2
|
||||
device ref pcie_rp11 on
|
||||
register "PcieRpClkReqSupport[10]" = "true"
|
||||
register "PcieRpClkReqNumber[10]" = "3"
|
||||
register "PcieRpClkSrcNumber[10]" = "3"
|
||||
register "PcieRpAdvancedErrorReporting[10]" = "true"
|
||||
register "PcieRpLtrEnable[10]" = "true"
|
||||
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 Sub Card" "SlotDataBusWidth2X"
|
||||
end
|
||||
end
|
||||
end
|
||||
Loading…
Add table
Add a link
Reference in a new issue