The changes focus on offering power state current thresholds, Thermal
Design Current (TDC) mode settings, and P-core and E-core hysteresis time
windows to support acoustic noise mitigation.
The Ps1Threshold, Ps2Threshold, and Ps3Threshold new fields configure
current thresholds for different power states. This allows for
fine-tuned power management by specifying current thresholds in 1/4 A
increments. These configurations can help optimize performance based on
specific current requirements for different components like IA, GT, and
SA.
The TdcMode parameter configures TDC mode based on the IRMS supported
bit from Mailbox, offering the option between iPL2 and Irms modes.
BUG=b:449662274
Change-Id: I949dd6a5c6bf575415ee62dcd0d0eda369ef29fc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89330
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
8f24546fc4