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vc/intel/fsp/fsp2_0/wildcatlake: Expose Thermal current thresholds and mode

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The changes focus on offering power state current thresholds, Thermal
Design Current (TDC) mode settings, and P-core and E-core hysteresis time
windows to support acoustic noise mitigation.

The Ps1Threshold, Ps2Threshold, and Ps3Threshold new fields configure
current thresholds for different power states. This allows for
fine-tuned power management by specifying current thresholds in 1/4 A
increments. These configurations can help optimize performance based on
specific current requirements for different components like IA, GT, and
SA.

The TdcMode parameter configures TDC mode based on the IRMS supported
bit from Mailbox, offering the option between iPL2 and Irms modes.

BUG=b:449662274

Change-Id: I949dd6a5c6bf575415ee62dcd0d0eda369ef29fc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89330
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jeremy Compostella 2025-09-24 09:52:13 -07:00 • committed by Jérémy Compostella
commit 8f24546fc4
1 changed files with 81 additions and 32 deletions
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113
src/vendorcode/intel/fsp/fsp2_0/wildcatlake/FspmUpd.h
View file

@ -2364,9 +2364,42 @@ typedef struct {
**/
UINT16 DcLoadline[6];
/** Offset 0x0896 - Reserved
/** Offset 0x0896 - Power State 1 Threshold current
PS Current Threshold1, defined in 1/4 A increments. A value of 400 = 100A. Range
0-152, which translates to 0-38A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA,
[3] through [5] are Reserved.
**/
UINT8 Reserved66[116];
UINT16 Ps1Threshold[6];
/** Offset 0x08A2 - Power State 2 Threshold current
PS Current Threshold2, defined in 1/4 A increments. A value of 400 = 100A. Range
0-48, which translates to 0-12A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA,
[3] through [5] are Reserved.
**/
UINT16 Ps2Threshold[6];
/** Offset 0x08AE - Power State 3 Threshold current
PS Current Threshold3, defined in 1/4 A increments. A value of 400 = 100A. Range
0-16, which translates to 0-4A. 0 = AUTO. [0] for IA, [1] for GT, [2] for SA, [3]
through [5] are Reserved.
**/
UINT16 Ps3Threshold[6];
/** Offset 0x08BA - Reserved
**/
UINT8 Reserved66[26];
/** Offset 0x08D4 - Icc Max limit
Voltage Regulator Current Limit (Icc Max). This value represents the Maximum instantaneous
current allowed at any given time. The value is represented in 1/4 A increments.
A value of 400 = 100A. 0 means AUTO. IA and GT, range 0-2047. SA range 0-1023.
[0] for IA, [1] for GT, [2] for SA, [3] through [5] are Reserved.
**/
UINT16 IccMax[6];
/** Offset 0x08E0 - Reserved
**/
UINT8 Reserved67[42];
/** Offset 0x090A - Thermal Design Current enable/disable
Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
@ -2376,7 +2409,7 @@ typedef struct {
/** Offset 0x0910 - Reserved
**/
UINT8 Reserved67[6];
UINT8 Reserved68[6];
/** Offset 0x0916 - Disable Fast Slew Rate for Deep Package C States for VR domains
This option needs to be configured to reduce acoustic noise during deeper C states.
@ -2398,7 +2431,7 @@ typedef struct {
/** Offset 0x0922 - Reserved
**/
UINT8 Reserved68[6];
UINT8 Reserved69[6];
/** Offset 0x0928 - Thermal Design Current time window
Auto = 0 is default. Range is from 1ms to 448s. <b>0: Auto</b>. [0] for IA, [1]
@ -2406,9 +2439,15 @@ typedef struct {
**/
UINT32 TdcTimeWindow[6];
/** Offset 0x0940 - Reserved
/** Offset 0x0940 - TDC Mode
TDC Mode based on IRMS supported bit from Mailbox. <b>0: iPL2</b>; 1: Irms. [0]
for IA, [1] for GT, [2] for SA, [3] for atom [4]-[5] are Reserved.
**/
UINT8 Reserved69[8];
UINT8 TdcMode[6];
/** Offset 0x0946 - Reserved
**/
UINT8 Reserved70[2];
/** Offset 0x0948 - DLVR RFI Enable
Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
@ -2416,9 +2455,19 @@ typedef struct {
**/
UINT8 DlvrRfiEnable;
/** Offset 0x0949 - Reserved
/** Offset 0x0949 - Pcore VR Hysteresis time window
0 is default. Range of PcoreHysteresisWindow from 1ms to 50ms.
**/
UINT8 Reserved70[13];
UINT8 PcoreHysteresisWindow;
/** Offset 0x094A - Ecore VR Hysteresis time window
0 is default. Range of EcoreHysteresisWindow from 1ms to 50ms.
**/
UINT8 EcoreHysteresisWindow;
/** Offset 0x094B - Reserved
**/
UINT8 Reserved71[11];
/** Offset 0x0956 - VR Fast Vmode ICC Limit support
Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds
@ -2443,7 +2492,7 @@ typedef struct {
/** Offset 0x096E - Reserved
**/
UINT8 Reserved71[28];
UINT8 Reserved72[28];
/** Offset 0x098A - PCH Port80 Route
Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
@ -2460,7 +2509,7 @@ typedef struct {
/** Offset 0x098C - Reserved
**/
UINT8 Reserved72[4];
UINT8 Reserved73[4];
/** Offset 0x0990 - PMR Size
Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
@ -2486,7 +2535,7 @@ typedef struct {
/** Offset 0x0997 - Reserved
**/
UINT8 Reserved73;
UINT8 Reserved74;
/** Offset 0x0998 - Base addresses for VT-d function MMIO access
Base addresses for VT-d MMIO access per VT-d engine
@ -2495,7 +2544,7 @@ typedef struct {
/** Offset 0x09BC - Reserved
**/
UINT8 Reserved74[20];
UINT8 Reserved75[20];
/** Offset 0x09D0 - MMIO Size
Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
@ -2510,7 +2559,7 @@ typedef struct {
/** Offset 0x09D4 - Reserved
**/
UINT8 Reserved75[36];
UINT8 Reserved76[36];
/** Offset 0x09F8 - Enable above 4GB MMIO resource support
Enable/disable above 4GB MMIO resource support
@ -2526,7 +2575,7 @@ typedef struct {
/** Offset 0x09FA - Reserved
**/
UINT8 Reserved76[10];
UINT8 Reserved77[10];
/** Offset 0x0A04 - Enable/Disable CrashLog Device
Enable or Disable CrashLog/Telemetry Device 0- Disable, <b>1- Enable</b>
@ -2536,7 +2585,7 @@ typedef struct {
/** Offset 0x0A08 - Reserved
**/
UINT8 Reserved77[20];
UINT8 Reserved78[20];
/** Offset 0x0A1C - Platform Debug Option
Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n
@ -2553,7 +2602,7 @@ typedef struct {
/** Offset 0x0A1D - Reserved
**/
UINT8 Reserved78[14];
UINT8 Reserved79[14];
/** Offset 0x0A2B - Program GPIOs for LFP on DDI port-A device
0=Disabled,1(Default)=eDP, 2=MIPI DSI
@ -2563,7 +2612,7 @@ typedef struct {
/** Offset 0x0A2C - Reserved
**/
UINT8 Reserved79[2];
UINT8 Reserved80[2];
/** Offset 0x0A2E - Program GPIOs for LFP on DDI port-B device
0(Default)=Disabled,1=eDP, 2=MIPI DSI
@ -2657,7 +2706,7 @@ typedef struct {
/** Offset 0x0A3D - Reserved
**/
UINT8 Reserved80[3];
UINT8 Reserved81[3];
/** Offset 0x0A40 - Temporary MMIO address for GMADR
The reference code will use this as Temporary MMIO address space to access GMADR
@ -2676,7 +2725,7 @@ typedef struct {
/** Offset 0x0A50 - Reserved
**/
UINT8 Reserved81[2];
UINT8 Reserved82[2];
/** Offset 0x0A52 - Enable/Disable Memory Bandwidth Compression
0=Disable, 1(Default)=Enable
@ -2706,7 +2755,7 @@ typedef struct {
/** Offset 0x0A56 - Reserved
**/
UINT8 Reserved82[2];
UINT8 Reserved83[2];
/** Offset 0x0A58 - Intel Graphics VBT (Video BIOS Table) Size
Size of Internal Graphics VBT Image
@ -2715,7 +2764,7 @@ typedef struct {
/** Offset 0x0A5C - Reserved
**/
UINT8 Reserved83[4];
UINT8 Reserved84[4];
/** Offset 0x0A60 - Graphics Configuration Ptr
Points to VBT
@ -2743,7 +2792,7 @@ typedef struct {
/** Offset 0x0A72 - Reserved
**/
UINT8 Reserved84[16];
UINT8 Reserved85[16];
/** Offset 0x0A82 - TCSS USB HOST (xHCI) Enable
Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
@ -2753,7 +2802,7 @@ typedef struct {
/** Offset 0x0A83 - Reserved
**/
UINT8 Reserved85[4];
UINT8 Reserved86[4];
/** Offset 0x0A87 - TCSS Type C Port 0
Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
@ -2785,7 +2834,7 @@ typedef struct {
/** Offset 0x0A8B - Reserved
**/
UINT8 Reserved86;
UINT8 Reserved87;
/** Offset 0x0A8C - TypeC port GPIO setting
GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined
@ -2853,7 +2902,7 @@ typedef struct {
/** Offset 0x0AC9 - Reserved
**/
UINT8 Reserved87;
UINT8 Reserved88;
/** Offset 0x0ACA - DLL Weak Lock Support
Enables/Disable DLL Weak Lock Support
@ -2863,7 +2912,7 @@ typedef struct {
/** Offset 0x0ACB - Reserved
**/
UINT8 Reserved88;
UINT8 Reserved89;
/** Offset 0x0ACC - Rx DQS Delay Comp Support
Enables/Disable Rx DQS Delay Comp Support
@ -2873,7 +2922,7 @@ typedef struct {
/** Offset 0x0ACD - Reserved
**/
UINT8 Reserved89[2];
UINT8 Reserved90[2];
/** Offset 0x0ACF - Mrc Failure On Unsupported Dimm
Enables/Disable Mrc Failure On Unsupported Dimm
@ -2883,7 +2932,7 @@ typedef struct {
/** Offset 0x0AD0 - Reserved
**/
UINT8 Reserved90[4];
UINT8 Reserved91[4];
/** Offset 0x0AD4 - DynamicMemoryBoost
Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is
@ -2901,7 +2950,7 @@ typedef struct {
/** Offset 0x0ADC - Reserved
**/
UINT8 Reserved91[9];
UINT8 Reserved92[9];
/** Offset 0x0AE5 - Vref Offset
Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
@ -2912,7 +2961,7 @@ typedef struct {
/** Offset 0x0AE6 - Reserved
**/
UINT8 Reserved92[2];
UINT8 Reserved93[2];
/** Offset 0x0AE8 - tRRSG Delta
Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
@ -3028,7 +3077,7 @@ typedef struct {
/** Offset 0x0AF8 - Reserved
**/
UINT8 Reserved93[41];
UINT8 Reserved94[41];
/** Offset 0x0B21 - Channel to CKD QCK Mapping
Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1
@ -3042,7 +3091,7 @@ typedef struct {
/** Offset 0x0B31 - Reserved
**/
UINT8 Reserved94[55];
UINT8 Reserved95[55];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration