The SMBus controller was previously disabled on the Lapis variant.
Enable the SMBus device in the overridetree to allow the system to
communicate with onboard peripherals like the SPD EEPROMs and
thermal sensors.
BUG=none
TEST=Build and boot on Lapis; verify smbus is initialized.
Change-Id: I9d7254b6c2686ec67392294d45b870e3670f2aca
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91196
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select HAVE_CHARGING_DEBUG_ACCESS_PORT for the Quartz variant.
BUG=b:474297115
TEST=Verified that quartz starts charging when the charger is connected
via the servov4.1 to the C0 port.
TEST=Verified that quartz starts charging when the charger is directly
connected to the C0 port.
TEST=Verified that the battery is charging by checking the battery
State of charge after 20-30 mins of charging.
Change-Id: Ie5e0d980780daa0adeee4e6a3e3525eb2616a29f
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
When the system is in a low-power boot state or early charging mode,
it is necessary to enable charging even when a debug access port
is connected. This ensures that developers can charge the
device while using the servov4.1 with the charger.
This patch updates the charging configuration to enable the debug
access sink by writing to the TYPE_C_TYPE_C_DEBUG_ACCESS_SNK_CFG
register.
BUG=b:474297115
TEST=Build Google/quartz
Change-Id: I155b071e678c8bc0ff0d719ac924b5026b21b37a
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91077
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add CONFIG_LP_DEFCONFIG_OVERRIDE_X64 flag to select default 64-bit
config file in payloads/libpayload/configs directory.
This is used in standalone environment. The existing libpayload
deconfig file is for boards with 32-bit format and deconfig_64
file is added for 64-bit without adding specific
board.[board name] file in libpayload.
BUG=none
TEST=Build with this new flag and check that the libpayload and
depthcharge.elf are built in 64-bit format.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Iac07cf9e3c11e49955c69553407be76ef4f8c060
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84107
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
This CL aims to make the code support ready before touchscreen launch.
BUG=b:483588481
TEST=build brox coreboot image
Change-Id: I9f8715311c976e92049ff3058920039c0d38ba3a
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
This CL aims to make the code support ready before touchscreen launch.
BUG=b:483762467
TEST=build nissa coreboot image
Change-Id: I919f92b782905ea9184203804f5ea095e37e9893
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add configuration for the PCIe Root Port connected to the WiFi 7 module.
BUG=b:481186489
TEST=Build successfully for moxoe. Verify WiFi 7 functionality on
moxie.
Change-Id: I8941b587ac35f6c03654de959cc93350b5604b35
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91103
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This is a reland of
commit c4be70f6ff ("commonlib/list: Support circular list").
In some use cases, we want to add items to the linked list and then
iterate over them with the insertion order. With the current API, the
call site needs to either use the inefficient list_append() function to
append items to the end of the list, or manually maintain a "tail"
node pointer.
To support that use case, add an internal helper function _list_init()
to initialize the list as a circular one with a placeholder head node.
_list_init() is automatically called within list_insert_after() and
list_append(). In list_insert_before(), an assertion is added to avoid
an insertion before the head node (which should be invalid). The
implementation ensures that the list is initialized as a circular one
whenever the first element is added. That also allows all call sites to
be auto-upgraded to the "circular list" implementation without any
modification.
Modify list_for_each() to support circular lists, and improve
list_append() efficiency by inserting the new node before the
placeholder head node. Also add a few assertions in the implementation.
Add a new test case to test iterating over an empty list.
Note that '(uintptr_t)ptr + (uintptr_t)offsetof(typeof(*(ptr)), member)'
was used instead of the simpler '&((ptr)->member)' because GCC9+ assumes
that the address can never be NULL. See commit 88991caf00
("include/list.h: Add support for GCC9+") for details. Now, with the
new list_for_each() implementation, that pointer value can never be
NULL.
Change-Id: Idc22887cce71284c9028dce10eeef9cc16669028
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90962
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Update the logo_bottom_margin for all fatcat variants from 100px to
200px. This adjustment ensures the OEM footer logo and associated
splash text are rendered higher on the screen, improving visibility
and alignment with updated UX requirements.
Modified variants:
- fatcat
- felino
- francka
- kinmen
- lapis
- moonstone
- ruby
Change-Id: Ia0f446768f1b0b13c09873176f79ed4418f28aa2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91155
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for dynamic text scaling based on the display resolution
to ensure bootsplash text remains legible on high-density panels.
Key changes:
- Implement get_resolution_scale() to determine a scaling factor (1x,
2x, or 3x) based on the panel's major dimension (HD, QHD, or 4K).
- Update draw_char() to render glyphs as scaled blocks, repeating each
font pixel across a square of the calculated scale factor.
- Apply the scaling factor to all text layout calculations, including
kerning, character advance, and total string dimensions.
- Ensure anti-aliasing (alpha blending) is correctly applied to each
individual pixel within the scaled blocks.
Change-Id: I8b22019ddaa46f1a24f38d565d946bb28a213791
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Transition the bootsplash text renderer from 1-bit monochrome bitmaps
to 8-bit alpha maps to support text smoothing (anti-aliasing).
Key changes:
- Update fonts.h to declare font_table as a 2D uint8_t array containing
alpha intensity values (0-255) for each pixel.
- Update draw_char() to perform alpha blending by mixing the text color
with the existing background pixel using the formula:
Result = (Color * Alpha + BG * (255 - Alpha)) / 255.
- Regenerate the font table data to reflect the new 8-bit format and
updated character widths.
Change-Id: I9d4dde74d86fd552b30523f3b8ff34fb8fdba782
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Update generate_font.py to produce 8-bit alpha maps instead of 1-bit
packed bitmaps. This enables text smoothing (anti-aliasing) during
framebuffer rendering by providing pixel intensity values (0-255).
Key changes:
- Switch PIL image mode from "1" (monochrome) to "L" (8-bit grayscale).
- Change C data type from uint32_t bit-packed rows to uint8_t byte arrays.
- Implement vertical centering logic using font metrics (ascent/descent).
- Add glyph clipping detection and warnings for both width and height.
- Format C output so each source line represents one glyph row.
Change-Id: Iec8a0123456789abcdef0123456789abcdef0123
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91178
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds platform-level support for dynamic splash screen text
rendering on ChromeOS devices. This implementation interfaces with the
ChromeEC to retrieve battery state-of-charge and charging status,
formatting these into human-readable strings during the bootsplash
stage.
TEST=Able to build and boot google/fatcat.
Change-Id: I5dc57d60cd6be0dc9c79668a8b1560d421e4d6cc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91095
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable rendering of system status messages during the `low-battery`
bootsplash sequence when `FRAMEBUFFER_SPLASH_TEXT` Kconfig is enabled.
This change adds a 32-byte buffer to capture platform-specific text
(such as battery status) and draws it at the footer of the framebuffer
alongside the logo.
TEST=Able to build and boot google/fatcat.
Change-Id: I298804869eb909201a9056b83e4954e223e2b9bb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Introduce FRAMEBUFFER_SPLASH_TEXT to allow rendering status messages
directly into the linear framebuffer. This enables displaying dynamic
information, such as battery levels or system status, during the
bootsplash stage without requiring complex graphics libraries.
Changes:
- Add Kconfig option to toggle framebuffer text support.
- User to call `render_text_to_framebuffer` to display the text message.
- Include render_text.c in ramstage build when
FRAMEBUFFER_SPLASH_TEXT is enabled.
- Create 24x32 font table entry using GoogleSansFlex_24pt-Medium.ttf.
TEST=Able to build google/fatcat.
Change-Id: I6ac25d8d8a9d3d77a9cc2f8c6e0139268b2066b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91092
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Expose calculate_logo_coordinates() by moving its declaration to
bootsplash.h and removing the static qualifier in render_bmp.c.
This allows other parts of the codebase, such as the upcoming text
rendering logic, to reuse the existing logo positioning math to
calculate destination coordinates based on alignment settings.
Change-Id: I8f8b767b093d6bc2befefdc55fe2effa38b95752
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91154
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update generate_font.py to support user-defined canvas width and height
via command-line arguments. This replaces the hardcoded 16x24 limits.
Key changes:
- Use argparse for --width and --height parameters.
- Ensure glyphs are left-aligned to the MSB (bit 15 or 31) for
scalability.
TEST=Able to create font table upto 32 pixels wide.
```
python generate_font.py <path_to_ttf> --width 24 --height 32 > font_table.c
```
Change-Id: Ifd02a979abf41a2c2b088ae58bb931f9f6421491
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91165
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure lapis to use coreboot (CHIPSET_LOCKDOWN_COREBOOT) to set BIOS
interface lock. Otherwise, FSP code will be responsible for locking the
chipset.
BUG=None
TEST=Able to build and boot lapis
Change-Id: Ia3a13390e4a1862164d820dd1ee220dea682a6a0
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
I would like to stay on track for everything regarding PantherLake,
given I'm working alongside Intel's engineers to support this SoC
properly.
TigerLake is just a formality, there are only two maintainers currently
and not many systems supported. I own the only TGL-H system in the tree
(erying/tgl) and ELDRID (Google/Volteer baseboard) with TGL-UP3.
Change-Id: I4849aa85787528086e247d9aec8be6138523f5a7
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Currently not all fixed MMIO ranges are advertised to the resource
allocator. This is not an issue as long bottom-up allocation is
used and as long as only small PCI BARs are present on the system.
Properly advertise all fixed MMIO ranges decoded by the PCH:
- RCBA
- TXT private
- TXT reserved
- TPM TIS
- LGMR
- HPET
Also remove subtractive decoding from IOAPIC and SPI ROM. Comments
indicate that there's an issue with the OS, but newer platforms also
don't set it to subtractive. No issue was seen with EDK2 payload and
Linux 6.8.8. As a side effect IOAPIC and SPI ROM are now marked as
reserved in e820, which should help payloads not aware of IOAPIC
and SPI ROM to behave more properly.
TEST=Still boots on Lenovo X220. No issues seen in coreboot or Linux.
New e820 reserved ranges:
[DEBUG] 15. 00000000fec00000-00000000fec00fff: RESERVED
[DEBUG] 16. 00000000fed00000-00000000fed00fff: RESERVED
[DEBUG] 18. 00000000fed1c000-00000000fed3ffff: RESERVED
[DEBUG] 19. 00000000fed45000-00000000fed91fff: RESERVED
[DEBUG] 20. 00000000ff000000-00000000ffffffff: RESERVED
Change-Id: I9c251a8c4a4403c5dc0ad535769d8d893dc64a05
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add new LDNs supported by the NCT6796D:
- 0x11: PGPIO, RI PSOUT Wake-Up
- 0x12: LED control
- 0x15: LED control 2
Change-Id: Icef4d32fad5430cbbe8ee4f3719d603361cfea95
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
The -96D is an updated version of the -91D and has additional LDNs.
This initial commit is a clone of the -91D with strings changed;
additional functionality will be added in subsequent commits.
TEST=tested with out-of-tree board Erying SRMJ4
Change-Id: I8f67c999f4076aaca52c93060a6a461dd9bcc62f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91100
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add extra_dump (-e) support for NCT6791D and NCT6796D to dump all HWM
banked registers: global, SYSFAN, CPUFAN, AUXFAN0, PECI calibration,
PECI setup, AUXFAN1–3 (+AUXFAN4 for -96D). Uses index port at base+5
and data port at base+6, per datasheets.
TEST=build/dump SIO registers for out-of-tree board Erying SRMJ4 with
NCT6796D.
Change-Id: I689374826bc1e38efaa3d68013610a8fa2052b1f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91098
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Per the NCT6791D datasheet, global configuration register 0x2d is
reserved, so exclude it from the dump like other reserved registers
(0x12, 0x15-0x19, 0x23, etc).
This was discovered when comparing datasheets for the -91D and -96D;
0x2d is a strapped register for the -96D, but reserved for the -91D.
Change-Id: I7d0372c4592f5532480acc5220ee11d9800d2277
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91097
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add SMM_TSEG_SIZE for Apollo Lake and Gemini Lake, set to same value as
used by other Intel SoCs. This is required since commit c078552e71
("soc/intel: Replace sa_get_tseg_size() with CONFIG_SMM_TSEG_SIZE")
removed the use of sa_get_tseg_size() without verifying that all SoCs
actually set the Kconfig being used to replace it.
TEST=build google/reef and verify CONFIG_SMM_TSEG_SIZE set in .config.
Change-Id: Iaac2eaddc6ef3ccfa299b8b10103d26d08881370
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Add support to invoke LPASS Initialization. Implement
voting-based enablement for the core HM GDSC and AON CC PLL
instead of direct control.
BUG=b:480195888
Test=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified LP0 BCM vote using serial logs.
Serial Log:
[DEBUG] BCM: Found address 0x00050048 for resource LP0
[INFO ] BCM: Successfully voted for LP0 (addr=0x00050048, val=0x60004001)
3. Verified if the clocks are enabled by taking clock dump. Clock
enablement is verified by dumping the 31st bit of the corresponding
clock’s CBCR register. A value of 0 in bit 31 indicates that the clock
is ON. The register details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
4. Able to boot X1P42100 w/o any adsp failed to bootup error.
Change-Id: I51ca2b7a5da8b35d0d8dd803000f1db28441c136
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The Birman+ evaluation board allows to test different display
connectors (HDMI, Displayport, ...) by plugin in different "NOVA"
cards. Every NOVA card has a small EEPROM identifying the connector.
Currently the graphics init isn't working with a DisplayPort
monitor connected to the DP NOVA card.
Fix the auto-detection code of the NOVA card. The code was swapping
the endianness of the connector_type which isn't necessary according
to the spec, but it looks like some cards where programmed with
different endianness.
To support both types, little and big endian, accept both for now.
TEST=Can boot into EDK2 with graphics enabled.
Change-Id: I54754967dd4887363043808116495cb36c636baf
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
cbfstool/flashmap/kv_pair.h uses the `__printf` macro. So we need to
include the header file defining `__printf` in the compilation.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I4ce98f59b94d64ef4e0694e0c83f7b83f6feec7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move LZ4 magic number definitions to public header file so that it can
be used in the payload. Also rename LEGACY_MAGICNUMBER to
LZ4_LEGACY_MAGICNUMBER for clarity when using from the payload.
BUG=None
TEST=Build Hylia BIOS image and boot to OS/UI.
Change-Id: Ief180105ec3fa7abf1013d0c5408aa96edde681b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91152
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Enable TCP0 alongside TCP1.
Test=build and boot adl/horizon, check there is video output over
USB-C.
Change-Id: I9db17fd3ed3e1eb0f6ea94320b595ce0d51f33e2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91168
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some of the entries were indexed wrong, so fix them.
Change-Id: I76890a3c3b2b30d8123a81352346776a656e8f7f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91167
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add configuration for the PCIe Root Port connected to the WiFi 7 module.
BUG=b:480035819
TEST=Build successfully for kulnex. Verify WiFi 7 functionality on
moxie.
Change-Id: I46dfe87afe7356cbe48cf15dd87a58b55a528094
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91071
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Before the PCIe features can be programmed FSP-S must set non
public bits in the EnumInitPhaseAfterPciEnumeration callback.
Violating this rule causes system instabilities and reboot loops,
depending on the selected features and hardware plugged into slots.
Since FSP-S can handle all types of PCIe features disable all of
them in coreboot and let FSP set the bits at the right time.
TEST=Can boot on AMD/glinda with ASPM L1SS enabled without seeing
system crashed.
Change-Id: Ib4c4597c91d6612018e4f55e1a989a676aff842d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91164
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select SOC_AMD_SUPPORTS_WARM_RESET on faegon only.
Glinda doesn't currently support warm resets.
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: Ic7a011827d16685bb3f2a13a576b7832a4929119
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The default CPU for birman_plus is STX1FP8 with a TDP of 28W.
Set SystemConfig to 2 to use the default IRM configuration
for 28W TDP CPUs and tweak slow PPT and fast PPT.
Change-Id: I555326228ad6a1dfa2f18c7fbd5a69b9b95b0f04
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Currently FSP modifies the AOAC bits of the FCH devices and
thus needs the current status passed via fch_rt_device_enable_map.
By default fch_rt_device_enable_map is 0, effectly disabling all FCH
devices, including the debug UART. This causes a hang at boot.
Fill fch_rt_device_enable_map in SoC code.
TEST=Can boot on amd/birman_plus again.
Change-Id: I00ef35ea6fe11939c4154940fef8cb902955fe27
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The existing logic prioritized the check for ENV_ROMSTAGE_OR_BEFORE
over the HAVE_EARLY_POWEROFF_SUPPORT configuration. This meant that
platforms with early poweroff support might still fall through to the
incorrect path depending on the boot phase.
Refactor the logic to:
1. Prioritize CONFIG(HAVE_EARLY_POWEROFF_SUPPORT) as the primary
mechanism for poweroff.
2. If early support is not available, check the environment stage:
- Perform standard pmc_control_poweroff() if after romstage.
- Halt with an emergency message if attempted too early in the
boot process without platform support.
This structure ensures that platform-specific early poweroff routines
are always preferred when configured.
TEST=Able to verify the AC host event is not getting cleared after
power-off.
Change-Id: Ieec8bcae5e1002d264db59cafe9236aaef6576e0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Moves the variables to more appropriate locations to save some lines and
make it more readable. For x86 it now also adds the intermediate, but
since x86 doesn't define any regions (e.g. ramstage) to check against,
the intermediate is effectively skipped.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I28371ae3416040243f238271ba45238ceccfcf0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90816
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A Windows driver bug resulted in the max98357a-tdm topology being
identified as the correct one, when in fact the non-TDM version is
correct. Now that the bug has been fixed, correct the speaker
topology. Linux was unaffacted as it uses a different mapping
method.
TEST=build/boot Win11 on RPL Taeko, verify audio functional out
of both left/right speakers and mixer functions properly.
Change-Id: I2f9cc7353540cd8722beada656a8c2a8b1ba8669
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91144
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When SMBIOS_TYPE4_SOCKETED_CPU is selected advertise upgrade
support in SMBIOS Type4 table.
Change-Id: I877c72592277690cdfa9ac6805697494c0e87b4e
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91146
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently the Sandybridge Lenovo devices are spending 25msec waiting
for ME to signal if RAM has been replaced. At the same time the RFID
I2C EEPROM needs to be locked, taking about 26msec.
By moving the locking to romstage the time spent waiting for ME can
be used to do something useful and thus reduce boot time.
TEST=On Lenovo X220 it boots 24msec faster.
Change-Id: Idd1f02a20dab6e422d55e3cf01d7b4a168792272
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Create the kulnex variant of the kuldax project by
copying the files to a new directory named for the variant.
BUG=b:480035819
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KULNEX
Change-Id: Ice06b67aeaa3bb8f36a6d3721014888defbfac15
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Create the moxoe variant of the moxie project by
copying the files to a new directory named for the variant.
BUG=b:481186489
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_MOXOE
Change-Id: I5dd9cc21b647834144cfffcd43bdcf84e9df3a0c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Ensure that BSP has latest microcode loaded before MPinit starts.
This aligns the code with other platforms ensuring that the microcode
on the BSP is up to date.
It likely has updated microcode before enabling NEM, so this is a
nop, but it also ensures that the microcode is located in CBFS
before the MTRRs are setup using x86_setup_mtrrs_with_detect() which
removes caching the SPI flash MMIO area.
Since intel_microcode_find() caches the microcode location
get_microcode_info() will be faster since it doesn't need to access
the CBFS.
TEST=Lenovo X220 still boots.
Change-Id: Ic4c5d1a06ce314b38b92e8a9c089ed901716ff27
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90893
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
