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MAINTAINERS: Add myself as maintainer for Intel TGL and PTL

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I would like to stay on track for everything regarding PantherLake,
given I'm working alongside Intel's engineers to support this SoC
properly.

TigerLake is just a formality, there are only two maintainers currently
and not many systems supported. I own the only TGL-H system in the tree
(erying/tgl) and ELDRID (Google/Volteer baseboard) with TGL-UP3.

Change-Id: I4849aa85787528086e247d9aec8be6138523f5a7
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Alicja Michalska 2026-02-10 19:20:17 +01:00 • committed by Matt DeVillier
commit ab42fceadc
1 changed files with 2 additions and 0 deletions
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MAINTAINERS
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@ -927,12 +927,14 @@ M: Pranava Y N <pranavayn@google.com>
M: Jayvik Desai <jayvik@google.com>
M: Avi Uday <aviuday@google.com>
M: Dinesh Gehlot <digehlot@google.com>
M: Alicja Michalska <alicja.michalska@9elements.com>
S: Maintained
F: src/soc/intel/pantherlake/
INTEL TIGERLAKE SOC
M: Subrata Banik <subratabanik@google.com>
M: Nick Vaccaro <nvaccaro@chromium.org>
M: Alicja Michalska <alicja.michalska@9elements.com>
S: Maintained
F: src/soc/intel/tigerlake/