The existing lanczos_weight() implementation naively follows the purely
mathematical definition for the `x == 0` special case. However, the
point of defining that special case is obviously to prevent division by
zero in the general case formula. Unfortunately we are still doing some
multiplications with `x` before we get to the division step, and our
fpmath library loses precision during multiplication. This can lead to
edge cases where `x` is not zero but `x_times_pi` later ends up being 0,
which causes the division to throw an exception after all. (I guess
we've just been lucky to not see this case in practice for now... it
requires the output pixel coordinate to be extremely close to but not
quite on the next input pixel coordinate, which may be rare in practice
with our scaling algorithms.)
This patch fixes the issue by implementing the special case later and
checking if `x_times_pi` is zero instead. Note that as long as we pass
this check, we can be confident that the division cannot fail even
though fpdiv() also truncates the divisor: this is because `x_times_pi`
was calculated from an fpmul() call with the constant fppi(), which has
34 significant bits. Even if x is the smallest possible non-zero value
after scaling for multiplication, the result `x_times_pi` must still
have 18 significant bits. That means it can be scaled down a further 16
bits for division without becoming zero.
Also add a simple unit test forcing exactly this condition to ensure the
code will not regress.
Change-Id: I2f212ee5df38252e97ec55aba3d2d25320c4b102
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
If DRIVERS_WIFI_GENERIC is disabled
`wifi_generic_cnvi_ddr_rfim_enabled` can't be found by the linker.
Additionally if there is no WIFI driver the CNVi DDR RFI Mitigation is
redundant.
Add DRIVERS_WIFI_GENERIC check around `CNVi DDR RFI Mitigation`.
TEST=Boot Intel Alder Lake-P RVP with DRIVERS_WIFI_GENERIC=N and
cnvi_wifi disabled
Change-Id: I4f89ef41a730e38e08886828db0d14f1277ccaf0
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Was inadvertently left out when this board was created.
TEST=build, verify ramstage.o created in variant subdir of build dir.
Change-Id: I3c728ba2abe94be4115a60d3a532cf0a19bec33c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add a CFR option to boot using the native panel resolution, rather than
a fixed/scaled video mode. This option selects between two VBT files:
one with the 'fixed mode' flag enabled, and one with it disabled.
This feature is mainly a workaround to a GNOME-related bug which
causes the creation of a 2nd display at the boot resolution. This
2nd display being a lower/different resolution than the native
panel resolution causes severe flickering/artifacting rendering
the display unusable unless this 2nd phantom display is disabled
on every boot.
Change-Id: I9e39258ce0171aab425150679d1ce30d69b2b1ef
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add a CFR option to boot using the native panel resolution, rather than
a fixed/scaled video mode. This option selects between two VBT files:
one with the 'fixed mode' flag enabled, and one with it disabled.
This feature is mainly a workaround to a GNOME-related bug which
causes the creation of a 2nd display at the boot resolution. This
2nd display being a lower/different resolution than the native
panel resolution causes severe flickering/artifacting rendering
the display unusable unless this 2nd phantom display is disabled
on every boot.
Change-Id: I275b5f8455fed58c0167e3a69db27bbc21577db0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87494
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
For boards for which set the 'Fixed Mode at boot' flag in the VBT, add
a CFR option to boot using the native panel resolution, rather than
a fixed/scaled video mode. This option selects between two VBT files:
one with the 'fixed mode' flag enabled, and one with it disabled.
This feature is mainly a workaround to a GNOME-related bug which
causes the creation of a 2nd display at the boot resolution. This
2nd display being a lower/different resolution than the native
panel resolution causes severe flickering/artifacting rendering
the display unusable unless this 2nd phantom display is disabled
on every boot
Change-Id: Ia75727f393744caf9062763e6118c1e2601512fa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Allows the Bluetooth RTD3 feature to be toggled on/off.
On some devices, enabling Bluetooth RTD3 causes the BT device to
continually disconnect/reconnect under Windows, so having the ability
to disable it in those cases is useful.
Change-Id: I1730dc35d56919fcf03acdf577288caf1e1a4ee3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Commit a959f0ad76 ("allocator_v4: Disable top-down allocation for
EDK2") disabled top-down allocation for edk2 due to a bug which broke
display init with Intel IGD. A workaround has been implemented in
MrChromebox's fork (and others) while the issue is being resolved
upstream, so re-enable top-down allocation unless upstream edk2
is being used.
TEST=build/boot various Google mainboards with edk2 payload selected.
Change-Id: I0e9b0d02bbf30878aef37a97d6a743a402700fc7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
When soft-disabled, boards selecting SOC_INTEL_CSE_LITE_SKU boot up
with a working state of M3_NO_UMA vs NORMAL, so handle this condition.
Without this, when vboot is not used, the board will simply fail to
boot as vboot_recovery_mode does not exist:
[ERROR] cse_lite: CSE does not meet prerequisites
[ERROR] cse_lite: Failed to get CSE boot partition info
[DEBUG] cse: CSE status registers: HFSTS1: 0x80032044,
HFSTS2: 0x32280126 HFSTS3: 0x50
[EMERG] cse: Failed to trigger recovery mode(recovery subcode:6)
This commit addresses the first error (does not meet prerequisites),
which allows CSE sync to continue and boot the RW partition in
the soft-disabled state. It also allows the CSE to properly transition
back into the normal working state (when that option is selected via
CMOS or CFR).
TEST=build/boot google/wyvern, verify able to disable/enable the ME
properly via CFR option.
Change-Id: I46da5ac248e267acee958d66ebbd97d945e722b9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87517
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
When soft-disabled, boards which select SOC_INTEL_CSE_LITE_SKU boot
with their working state having a value of M3_NO_UMA (0x4), as
opposed to the "normal" value of M0_NO_UMA (0x5). Add a define for
this value (taken from older ME code in coreboot) and add a function
to check if the CSE is in that state, which will be used in a
subsequent commit.
TEST=tested with rest of patch train
Change-Id: I405987ece00b3849a9fcdf1bfc8b377fd8d010dc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87516
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit refactors the configuration options for Intel
Panther Lake SoC variants to improve clarity and maintainability.
Key changes:
- Introduce a new SOC_INTEL_PANTHERLAKE configuration option to
serve as a base selection for all Panther Lake SoC variants.
- Update SOC_INTEL_PANTHERLAKE_U_H and SOC_INTEL_PANTHERLAKE_H to
select SOC_INTEL_PANTHERLAKE instead of
SOC_INTEL_PANTHERLAKE_BASE.
- Update existing code to utilize the new SOC_INTEL_PANTHERLAKE
guard where Panther Lake variant guards are applied.
BUG=b:394208231
TEST=Build Ocelot and Fatcat and verify it compiles without any error.
Change-Id: I656006dab6f08c9a16996ad194fa0b5b751f91aa
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87511
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The original SPMI calibration process is only suitable for pre-MT8189
SoCs. Update the flow to also support MT8189.
BUG=b:379008996
BRANCH=none
TEST=build pass and driver log is normal:
[INFO ] [Pass] dly:1, pol:0, sampl:0x2
[INFO ] [Pass] dly:1, pol:0, sampl:0x2
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I636b3062fc25fc1d7d39e3426602e6434be4c26a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87508
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some of MTK's ICs (such as the MT8189) use two eFuse registers to
record CPU ID information.
Users can use get_cpu_id and get_cpu_segment_id to obtain the SoC
version. For example, the CPU ID of the MT8189H is 0x81890000, and
the CPU segment ID is 0x21.
BUG=b:379008996
BRANCH=none
TEST=build pass
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I535874025cde7f6f975246105e32e165083601e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87509
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The previous commit incorrectly set GPIO register address due to a lack
of checking. This commit fixes the register address to ensure GPIO
function can work well.
BUG=b:379008996
BRANCH=none
TEST=build passed, and check SD card can be identified in depthcharge
firmware-shell: storage init
Man 000002 Snr 1759900928 Product SA02 Revision 9.12
* 0: UFS LUN 0
1: removable mtk_mmc
2 devices total
Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com>
Change-Id: I14125ff331f965ce8cbb83cb25d8a2feff0359f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87510
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disks larger than 2TB (technically disks with more than 2^32 blocks, but
for the common block size of 512 that comes out to 2TB) cannot represent
their full amount of blocks in the SCSI READ_CAPACITY(10) command used
by libpayload's USB mass storage driver. The entire driver isn't written
to support block addresses larger than 32 bits anyway.
The SCSI command has been designed in a clever way so that devices are
supposed to return the maximum value (0xffffffff) if the actual value
doesn't fit. However, our code adds one to the value (because it is
actually the address of the last block, but we want to know the number
of blocks). This makes it overflow back to 0 which is not great.
This patch caps the result before incrementing it so that the overflow
cannot occur, allowing us to at least access the first 2TB of super
large USB sticks.
Change-Id: Ic445923b7d588c4f523c4ed95a06291bc1969261
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
I found duplicated code masking stack pointer.
So, i'd like to remove the duplicate for refactoring :-).
This is my build output of c_start.o, before vs after modifying.
before modifying
...
44: f3 ab rep stos %eax,%es:(%edi)
46: bc 00 00 00 00 mov $0x0,%esp
4b: 83 e4 f0 and $0xfffffff0,%esp
4e: b0 6e mov $0x6e,%al
50: e6 80 out %al,$0x80
52: 83 e4 f0 and $0xfffffff0,%esp // deleted.
55: e8 fc ff ff ff call 56 <_start+0x56>
...
after modifying
...
44: f3 ab rep stos %eax,%es:(%edi)
46: bc 00 00 00 00 mov $0x0,%esp
4b: 83 e4 f0 and $0xfffffff0,%esp
4e: b0 6e mov $0x6e,%al
50: e6 80 out %al,$0x80
52: e8 fc ff ff ff call 53 <_start+0x53>
...
P.S. it is commits which introduced duplication.
32bit : 4d75dbd1c1
64bit : 1c4c7ad1e5
Change-Id: I417ce90279fea4b00432e6a209f77a6dd0c0fee6
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Add a header with a CFR object for setting the coreboot console log
level, so that all mainboards can make use of it without duplication.
Change-Id: I473421e0e6b2031eb9846f5a798b427104dc3af3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Commit 12abfb43dc ("soc/intel/cnvi: Add CNVW OpRegion") added an
ACPI function call to \_SB_.PCI0.GPCB(), which is present in the SoC
common northbridge.asl, but not in the ApolloLake northbridge.asl.
Add the missing GPCB function to the APL northbridge. Per Intel doc
336561, the PCIEXBAR starts at bit 28 vs 26 on other platforms.
TEST=build/boot google/ampton, verify no ACPI errors in dmesg related
to missing function/object, Windows boots without ACPI_BIOS_ERROR BSOD.
Change-Id: Ib45d655a30bf68e9b3d24a444c505e515c4950a6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87486
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The HDMI output was not enabled and therefore not functional; enable
it on port DDI-B as per the schematics.
TEST=build/boot Ubuntu 24.10 on starlabs/starbook adl-n, verify
HDMI output functional when connected at boot and when hotplugging.
Change-Id: I746eb1c2284778d46ee5d5a85dae41f284254cb0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87491
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit addresses a performance issue on the Panther Lake H SoC by
disabling the EnableFastVmode setting in addition to the CepEnable
setting. It was discovered that merely disabling CepEnable was
insufficient, as the FSP continued to program Panther Lake U IccLimit on
FastVMode capable boards, causing performance degradation under
high-stress conditions. By also disabling EnableFastVmode, the I_TRIP
value is prevented from being set lower than the device's actual
capability.
TEST=Verify that IccLimit is programmed with FSP default values.
Change-Id: I2974f1311b69f283d7fa4982c28a9037a8ab23f7
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Hook up `Device4Enable` FSP setting to devicetree state and drop its
redundant devicetree setting `Device4Enable`. For boards where the
register setting and PCI device status are not in agreement, use
the register setting to determine the PCI device status, since that
is what FSP uses.
Modeled after similar patches for other SoCs.
Change-Id: If17e6e86f6933b334e13f2c05ca513cef0998996
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87483
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some mainboards use the common DPTF ASL rather than the DPTF chip
driver, and those boards need to skip generation of the TCPU ACPI
device in order to avoid a duplicate being created and causing
issues with ACPI table parsing. Create a Kconfig that affected
boards will select to skip generating the TCPU in the SSDT.
Change-Id: Iec58d480821a273cdb4ff086f4995d21fd4bdb2e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The GNU assembler allows to use arithmetics on constant expression,
except for division using the '/' character. By default the '/'
introduces a line comment, see [1]. This behaviour can be changed when
the command line argument --divide is being used. However that's not
the case for coreboot.
Since the divide doesn't work as expected the assembler generates 512
times as much instructions on the .rept evaluation than it should. This
didn't cause any problem since it only filled PML4E, but the additional
entries pointed to non existing PDPTs. As long as the memory above 512GB
wasn't accessed it worked just fine.
Use shifts to fix the arithmetic and thus generate only the expected
number of page table entries. Required for the following patch, which
walks page tables and expects to find sane directories.
1: https://sourceware.org/binutils/docs-2.26/as/i386_002dChars.html#i386_002dChars
TEST=GAS generates 512 times less entries on .rept evaluation
Change-Id: I480142df010bf4e7d6fb84c9891e93b6ee21e908
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87356
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
NUM_COMx_GRP_PADS value is calculated based on COMx_GRP_PAD_END
and COMx_GRP_PAD_START values instead of using GPIO pin names.
TEST=Compiled and Verified on Wildcat Lake Simulation Platform.
Change-Id: I0c5b2ebc00f328bd4b9df4653d5339781e38fcba
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add UCSI port data/port location data which is required for Windows to
use UCSI.
Adjustments taken from EC ACPI on Dell 5400/7410 Windows devices.
TEST=build/boot google/drallion, verify type-C ports functional under
Windows 11.
Change-Id: I04aa87ec10f320d1740cd3897864d154f2aea507
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87489
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Only run _REG on attach
- Reinitialize on WAK to support S3 / Hibernate
Adjustments taken from EC ACPI on Dell 5400/7410 Windows devices.
TEST=build/boot google/drallion, verify S3 sleep works properly as
well as S0ix.
Change-Id: I162d02c7d3c81f1106ddc65a3804f7112dda66b2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87488
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Key changes:
- Relocate the package corresponding to CPUJTAG group from GPI3
device to the GPI4 device in the ACPI table, utilizing a Kconfig
guard for conditional compilation.
- Add ACPI IDs specific to Wildcat Lake GPIO communities.
- Select SOC_INTEL_PANTHERLAKE_BASE for SOC_INTEL_WILDCATLAKE to
clearly differentiate between Panther Lake and Wildcat Lake
changes.
References:
- Wildcat Lake EDS Volume 2 (#829345)
- Wildcat Lake GPIO Implementation Summary (#836031)
BUG=b:394208231
TEST=Both Ocelot and Fatcat variants are built
Change-Id: I934c193c75e459c72cc8b01a575cc0bbd65dc273
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This patch introduces GPIO changes for the Wildcat Lake SoC.
These changes coexist with the Panther Lake SoC GPIO files.
Key Changes:
- The CPUJTAG group is moved from community 3 to community 4.
- A new pin is added to Group H.
- Wildcat Lake-specific register definitions are included.
- Kconfig is utilized to segregate Wildcat Lake GPIO changes.
References:
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
- Wildcat Lake GPIO Implementation Summary (#836031)
BUG=b:394208231
TEST=Both Ocelot and Fatcat variants are built
Change-Id: Ib364d41097c53cd085c6cf89b0461ce38117b21e
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87452
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Sending the disable and EOP commands will not work if flash descriptor
override is set on Meteor Lake.
Change-Id: I3b5a56229434c9cc326141d48359faa7759541ee
Signed-off-by: Jeremy Soller <Jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
This makes Bluetooth RTD3 runtime configurable.
Change-Id: I467634e013a140e0a39802d2a1767583ba33a76e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit updates the pre-allocated IGD stolen memory size for Intel
Panther Lake SoCs from 128MB to 64MB within the FSP-M configuration
parameters.
Reducing the IGD stolen memory allocation from 128MB to 64MB
significantly optimizes system memory resource utilization (by 64MB).
Furthermore, this reduction frees one MTRR. Previously, the 128MB IGD
allocation consumed all 10 available BIOS MTRRs; the new 64MB allocation
now leaves MTRR index 9 available.
BUG=b:413638298
TEST=Able to boot google/fatcat to OS w/ internal and/or external
display attached.
Change-Id: Ifd60973bc5d37cbbc4ea6c8eaf5d851069d53083
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87460
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use an additional Realtek NIC MAC programming sequence recently
added to drivers/net/r8168.c.
BUG=https://ticket.coreboot.org/issues/579
TEST=Specified MAC address now recognized and retained by Linux r8169
driver without further work.
Change-Id: Ia1409874920b2e598e8b8b3c186fc46bd0cef296
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87437
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On mainboard/asus/p8z77-v_le_plus, programmed MAC address is being
reverted with controller resets done at loading and unloading of Linux
r8169 kernel module.
Ghidra examination of vendor BIOS reveals an additional sequence to
program the MAC address into its ERI register block. This patch
adds code to replicate that sequence, gated by a Kconfig so it's
only included where necessary.
BUG=https://ticket.coreboot.org/issues/579
TEST=When applied with mainboard level changes in CB:87437, specified
MAC address now recognized and retained by Linux r8169 driver without
further work.
Change-Id: Iae33e24e564f9fba52acb16138fe89085d9eeb03
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87436
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use a static variable to cache the board ID. It optimizes boot time by
reading the ID once per stage and retaining it for subsequent use.
Rewrite the function to avoid the unnecessary ChromeEC wrapper function.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I166ca1abdf7838f91319d0bcf11354055ed93eef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87247
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Ziliatech SDVB8D8A34XGCL3N3T as id 2, resulting in the list below:
DRAM Part Name ID to assign
MT53E512M32D1NP-046 WT:B 0 (0000)
K4U6E3S4AA-MGCR 0 (0000)
H54G46CYRBX267 0 (0000)
CXDB4CBAM-ML-A 1 (0001)
SDVB8D8A34XGCL3N3T 2 (0010)
BUG=b:398700043
BRANCH=None
TEST=Use part_id_gen to generate related settings
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: If85ea78828ab520d10dcbe4ccbba685ac1746c51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87440
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit introduces a Kconfig option to define the GPIO pin used
for the Google Security Chip (GSC) to Application Processor (AP)
interrupt on the Bluey mainboard.
Previously, the GPIO_GSC_AP_INT was hardcoded to GPIO 34 in
board.h. This change makes it configurable for any future variants
using Qualcomm X1P-42-100 SoC.
BUG=b:404985109
TEST=Successfully built google/bluey with the Qualcomm x1p42100 SoC.
Change-Id: I5759667158082a80124bf3faa3c56aee50c1be34
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit implements `mainboard_is_hda_codec_enabled` for the Google
Francka mainboard variant. This overrides the default weak HDA common
initialization.
Initialization of the High Definition Audio (HDA) controller, managed by
`azalia_audio_init()` (which handles HDA verb table loading), is now
conditional. It proceeds only if the firmware config
`FW_CONFIG(AUDIO, AUDIO_ALC256M_CG_HDA)` is set. This targets the
ALC256M-CG HDA codec.
This change ensures that HDA verb tables are loaded only when the
ALC256M-CG HDA codec is actively configured for the Francka variant.
Crucially, this prevents attempts to incorrectly load HDA verbs for
other audio interfaces, like SoundWire (SNDW), which might be present
in different Francka hardware configurations.
The header `intelblocks/hda.h` added to support this HDA initialization
logic.
BUG=b:ENTER_FRANCKA_BUG_ID_HERE
TEST=Verified HDA verb table loading is skipped on Francka platforms
when configured with non-HDA audio codecs (e.g., SNDW),
and proceeds as expected when ALC256M-CG HDA is configured
Change-Id: Idbc506c1ad180c7e8ecdec51c3491e6f0518204c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit implements `mainboard_is_hda_codec_enabled()` for the
Google Fatcat mainboard variant. This overrides the default weak HDA
common initialization.
Initialization of the High Definition Audio (HDA) controller,
managed by `azalia_audio_init()` (which handles HDA verb table
loading), is now conditional. It proceeds only if the firmware
config `FW_CONFIG(AUDIO, AUDIO_ALC256_HDA)` is set. This value
(3) specifically targets the ALC256 HDA codec.
This change ensures that HDA verb tables are loaded only when the
ALC256 HDA codec is actively configured for the Fatcat variant.
Crucially, this prevents attempts to incorrectly load HDA verbs
for other audio interfaces, like SoundWire (SNDW) or I2S, which might
be present in different Fatcat hardware configurations.
The header file `intelblocks/hda.h` added for this. As a minor stylistic
update, header inclusions in this file are also alphabetized.
BUG=b:413638298
TEST=Verified HDA verb table loading is skipped on Fatcat platforms
when configured with non-HDA audio codecs (e.g., SNDW, I2S),
and proceeds as expected when ALC256 HDA is configured.
Change-Id: Ifc158b7d15c763cc07d28154259b7e64709bea16
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit refactors the HDA initialization within the common Intel
SoC block to provide mainboard-level customization.
A new weak function, mainboard_is_hda_codec_enabled(), is
introduced. The `hda_init()` function invokes `azalia_audio_init()` when
`CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB)` is enabled and
`mainboard_is_hda_codec_enabled()` is also true.
The default (weak) implementation of `mainboard_is_hda_codec_enabled()`
simply returns `true`, ensuring that the original behavior is maintained
for mainboards that do not provide an override.
This change allows specific mainboards to implement their own
`mainboard_is_hda_codec_enabled()` to specify if hardware design has
support for HDA codec depending upon the firmware config (FW_CONFIG) for
the audio subsystem.
BUG=b:413638298
TEST=Able to build and boot google/fatcat.
Change-Id: Ided1413e828f6bc3421e538a969c38e15b5f3116
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit removes the `device ref npk on end` from the
`overridetree.cb` files for the `fatcat` and `francka` variants
of the `google/fatcat` mainboard. This effectively disables
the NPK device for these configurations (because `npk` is default
set to disable).
BUG=b:328770565
TEST=Able to build google/fatcat.
Change-Id: I9dda20552781af6b29a2156cbc1e3bea352c5836
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
GPP_E9 was wrongly configured to NF1 instead of NF2 i.e. ISH_GP4.
Reference: Intel doc#648094
BUG=b:410645679
TEST=Check GPIO config in the OS.
Change-Id: I43e3ec2e29138d59ed82e5ff4b264ab8dc3a39fb
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87471
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yuval Peress <peress@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit imports changes from mb/google/fatcat to mb/intel/ptlrvp as
of coreboot codebase commit 010cfa2842
("doc/internals/devicetree_language: multiple segment groups
supported").
Here is the list of imported commits:
- commit 9495063993 ("mainboard/google/fatcat: Fix SMBIOS Processor
upgrade info")
- commit 27f3427f4a ("mb/google/fatcat/var/fatcat: Update GSPI0 CS pin
for FPS")
- commit c41af2d43c ("mb/google/fatcat/var/fatcat: Update THC
Interrupt for Touchpad Development")
- commit b5dea9fa99 ("mb/google/fatcat/var/francka: Add Write Protect
GPIO to cros_gpios")
- commit ef80ccbc43 ("mb/google/fatcat: Disable EC software sync for
Microchip EC")
- commit 9f39d6ec5e ("mb/google/fatcat: Enable HAVE_SLP_S0_GATE for
felino and francka")
- commit eb85dfae1f ("mb/google/fatcat: Configure GPIO_SLP_S0_GATE for
francka and felino")
- commit 0fc2422e88 ("mb/google/fatcat: Implement S0ix hooks aka
`MS0X` method")
- commit 1fa5ab805b ("mb/google/fatcat: Remove unnecessary CNVi core
variables settings")
- commit 5c0340349e ("mb/google/fatcat: Rationalize Wi-Fi and
Bluetooth combinations")
- commit 275beb93db ("mb/google/fatcat: Conditionally check for barrel
charger")
- commit e9b020f02e ("mb/google/fatcat: Allow board-specific FSP-M UPD
override")
- commit 3a88eb8cb6 ("mb/google/fatcat: Enable HDA SDI based on FW
config")
- commit 0ac2058dbe ("mb/google/fatcat: Increase sagv_freq_mhz for
work point #1 to #3")
- commit 6e529e7c06 ("mb/google/fatcat: Add Intel Touch support for
touchscreen and touchpad")
Overall, these commits aim to improve the configuration, performance,
and compatibility of the Intel Panther Lake Reference Validation
Platform (PTLRVP) mainboard across various aspects, including processor
upgrade support, peripheral integration, power management, and audio
functionality.
TEST=Successful boot with a ptlrvp image on a Fatcat board.
Change-Id: Ie27763a367d8d53c64ad78d26909f1068af3c819
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87223
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On recent AMD platforms the VRT bit in the StatusD register is
read-writeable and set every 1024msec when RTC power is good.
This leads to a timeout in RtcWaitToUpdate() waiting for the bit
to be set and the gEfiRealTimeClockArchProtocolGuid won't be installed.
The protocol is critical to boot.
Adjust the code to not clear the VRT bit, as RtcWaitToUpdate() will
return an error, as it assumes the VRT bit is read-only and hardwired
to one as on Intel ICHs. While the timeout could be increased it
would also increase boot time by up to a second.
On platforms where the VRT bit is read-only the introduced code
does the same as before.
Change-Id: I8bc432114c83fa5f5fb35a144e3a35c38ee8a3de
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87415
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Update the DPTF parameters as provided by thermal team.
1. Tcc_offset: 5 -> 3
2. Modify critical policy and passive policy setting
BUG=b:411866724
BRANCH=firmware-trulo-15217.771.B
TEST=build test firmware and verified by thermal team
Change-Id: Id5fda2e8c4985d41d0871454bb808a9cdfedc3e6
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87425
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
This commit adds configurations for both external and internal EC
versions of the PTL RVP board. The changes involve updates to the
Kconfig files to select appropriate EC configurations based on the
specific PTL RVP variant. By organizing these options, it ensures
that the build system selects the right EC components and
configurations, aligning with the specific needs of the board version
in use.
The new configuration for external EC (`BOARD_INTEL_PTLRVP_CHROMEEC`)
enables Chrome EC related config options and enables TPM, whereas
Intel EC (`BOARD_INTEL_PTLRVP`) disables Chrome EC related config
options and uses MOCK TPM.
BUG=none
TEST=Build the firmware for PTL RVP with both external and internal EC
settings, verifying that the correct components are included based on
the chosen configuration. Ensure that the board operates correctly
with the selected EC setup.
Change-Id: Ic3e40f2a19d7ed4f7a16e6e516a284a9a778b9fd
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add GOOGLE OCELOT MAINBOARDS section for src/mb/google/ocelot and
update the maintainers list to add Nick Vaccaro, Pranava Y N, and
Avi Uday as maintainers.
Change-Id: Ia5fc7fcdd5ea2f3588343834dccd86ee2b17f9a8
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87438
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
