The memlayout.ld for X1P42100 was copied from a previous SoC and
lacked clear documentation about the platform's specific memory
organization.
This commit adds a detailed ASCII art diagram that provides a visual
representation of the complete memory map. The diagram clarifies the
locations of all major regions, such as AOPSRAM, SSRAM, BSRAM, SHRM,
and the various DRAM segments, which greatly improves the clarity and
maintainability of the linker script.
TEST=Builds successfully for x1p42100.
Change-Id: Ia1714f8da25a22a13f5960d056df33463dd99f31
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88783
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch fixes a bug in load_and_render_logo_to_framebuffer where the
logo_bottom_margin was only correctly applied to the NORMAL
orientations.
For other orientations, the margin was incorrectly applied, resulting
in the logo not being positioned as expected.
TEST=Able to see logo footer in alignment with the logo center while
booting google/felino.
Change-Id: Ia886ef5305166b1307fcf5b0acd12582b4b6ad80
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
CPR image is required by Qclib for PMIC initialization. This patch adds
support to pack and load the CPR binary, reserves memory for CPR
settings in the memory layout and adds CPR entry in if_table which
is passed to Qclib.
TEST=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified using CPR load log from coreboot.
```
[INFO ] CBFS: Found 'fallback/cpr' @0xa3900 size 0x46d in mcache
@0x1485e340
[INFO ] VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
supported for secdata_kernel v0, return 0
[INFO ] VB2:vb2_digest_init() 1133 bytes, hash algo 2, HW acceleration
forbidden
[INFO ] CBFS: Found 'fallback/shrm_meta' @0xebb80 size 0xb0d in mcache
@0x1485e7c0
```
Change-Id: I58161a1d05222c84e077ada1024db50440e783f1
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88870
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CPR image is required by Qclib for PMIC initialization. This patch
adds support to declare cpr_settings region and create CBFS prefix
for CPR.
Change-Id: Ia92717715eacaf05d33db040d99cf81d8d288111
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88869
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add 2 memory parts in mem_parts_used.txt, and generate SPD id
for these parts.
1. H58G56CK8BX146 (Hynix)
2. MT62F2G32D4DS-023 WT:C (Micron)
BUG=b:422831379
TEST=Run part_id_gen tool and check the generated files.
Change-Id: Ia6ee285f558a456c423586ccd7e970d14dd3cfea
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Some SSDs block the CPU from reaching PC10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
Disable GPP_F20 (EN_PP3300_SSD) and GPP_H23 (SRCCLKREQ#5) by fw_config
for Non-SSD sku.
BUG=b:435567235
TEST= emerge-brox coreboot
suspend_stress_test verify that the device suspends to S0ix.
suspend_stress_test w/o this CL
(with Kioxia PCIE Gen4 SSD KBG60ZNV512G)
Suspend failed, pc10 count did not increment from 0
Package C-States Now :
Package C2 : 26205917
Package C3 : 0
Package C6 : 0
Package C7 : 0
Package C8 : 0
Package C9 : 0
Package C10 : 0
Substate Residency
S0i2.0 0
S0i3.0 0
suspend_stress_test w/ this CL
Device suspends to S0ix.
Substate Residency
S0i2.0 0
S0i3.0 12020538
Change-Id: Iecffa89ae7865bc63b1b0dd974a439f35e9ca7f4
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88771
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-by: sridhar siricilla <siricillasridhar@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
In the scenario of suspend, when the SPM firmware attempts to turn off
the VDDQ and VMDDR power supplies, the command sent is rejected by PMIF,
resulting in a system hang. The reason is that SPM simultaneously wrote
two registers (two bytes), while the original configuration only allowed
reading or writing one byte at a time.
Modify the maximum number of bytes that an SPMI user can read or write
in a single operation to meet the requirement of reading or writing 16
bits at once.
BUG=b:420874944
BRANCH=skywalker
TEST=2-byte R/W passed; suspend-resume verified successfully.
Change-Id: I46ace45564328c46ab340b74d73e3574957e36ef
Signed-off-by: Niklaus Liu <niklaus.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88790
Reviewed-by: Vince Liu <vince-wl.liu@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Niklaus Liu <niklaus.liu@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Some eDP panels assert HPD (Hot Plug Detect) after panel VCC is enabled,
typically around 200ms. To reduce boot time, this commit replaces the
original fixed 200ms delay with polling for the HPD status, shortening
the waiting period to approximately 70ms.
Once the HPD pin is detected high, an additional delay of around 1ms is
introduced to ensure the AUX channel is ready for EDID reading.
BUG=b:434574691,b:439535227,b:439476647
BRANCH=none
TEST=Check firmware display on Navi and Skywalker
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I6702c79416700b44d4bfbc763b6fc6003feb69b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88864
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This change addresses GCC-15 behavior where {0} union initializers only
clear the first member, leaving padding bits uninitialized. The new {}
initializer ensures full union clearing as required by C23.
Change-Id: I1d2761856e0c9bf9cc7045cc8e3af622582bd1ed
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88860
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This script will warn and suggest fixes when a CB:<change-id> of an
already merged change is found in the commit message. This should
enforce the clarification that was added to the documentation in
CB:88776.
This script requires a JSON parser (i.e. jq) to parse Gerrit's
REST API[1]. While it may be possible to grep the values, we chose to
use a proper parser to ensure there would be no false-positives.
TEST=
Prepare a commit with the following commit message:
Here are some open changes: CB:88614 CB:88717 CB:87282
Here are some abandoned changes: CB:88413 CB:84504 CB:82136
Here are some merged changes: CB:88566 CB:88598 CB:88697
Here are some old merged commits: CB:1 CB:50 CB:950
Here are some wrong stuff: CL:100 CB:TEST CB:99999
The script produces the following result (may change in the future when
open changes are merged etc):
Using a change ID (CB:88566) for an already merged commit; please replace it with:
commit 21639c3771 ("mb/getac/p470: Use common gpio functions")
Using a change ID (CB:88598) for an already merged commit; please replace it with:
commit 05a38e2af3 ("mb/google/fatcat: Disable memory training progress bar")
Using a change ID (CB:88697) for an already merged commit; please replace it with:
commit 1da2f46db8 ("soc/intel/alderlake: Restore mem_init_override_channel_mask()")
Using a change ID (CB:1) for an already merged commit; please replace it with:
commit 140a990a61 ("Teach abuild to emit JUnit formatted build reports")
Using a change ID (CB:50) for an already merged commit; please replace it with:
commit 7c634ae8c1 ("msrtool: added support for Intel CPUs")
Using a change ID (CB:950) for an already merged commit; please replace it with:
commit c31384e62c ("Fix up Sandybridge C state generation code")
CB:99999 does not exist
[1] https://gerrit-review.googlesource.com/Documentation/rest-api.html
Change-Id: I1c72f739b1f47b1227ef1e158b1553aa56945d7e
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This should address the following open action item from the coreboot
leadership meetings[1]:
> Add clarification to docs, "do not use gerrit change-id or CB: format
> in reference to already-merged patches".
[1] https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/YCA55MINAFK5M56OAUA2NMM7WDMDEGXI/
Change-Id: Ie742caca70e284254bb7f8a070c3a441b6a80c58
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88776
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extracted ICR wait logic into a new function 'icr_wait_timeout'.
Change-Id: Ie48899f7afb125061fd7efd44c83f5775c05d254
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Cover the SPIROM with a temporary MTRR to speed up SPI flash accesses
after MPinit has removed the MTRR that was installed for postcar stage.
TEST=Booted on Lenovo X220 and measured using cbmem -t:
Before:
16:finished LZMA decompress (ignore for x86) 1,391,520 (366,351)
After:
16:finished LZMA decompress (ignore for x86) 1,218,418 (210,054)
Boots 156msec faster than before.
Change-Id: Ia3df06b5c2a09e05c76361f3e38be83475122ee7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88811
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clear DF flag before invoking MOVS instruction to make sure it
increments %esi/%edi on each mov.
Change-Id: I209f50dec2003ea9846e5958d3e77b8979f338df
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88796
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
from the project's Releases.md file:
* Prefer PCI IO allocations above 4Gig on 64bit capable machines.
* Multiple simultaneous USB keyboard and mouse support.
* Legacy support for internally generated ACPI tables has been removed.
* SeaVGABIOS support for VBE get/set palette data.
* Several bug fixes and code cleanups.
TEST=Successfully booted lenovo/t530
Change-Id: Ie1f0620ce46ebdafc84e8e13a79aa21c0526c235
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Config GPIO GPIO_AP_EDP_BKLTEN as output low. When skipping firmware
display, it can prevent leakage to GPIO_AP_EDP_BKLTEN and cause it
to be pulled up to a 0.6 V step.
BUG=b:438353560
BRANCH=none
TEST=skip fw display check GPIO_AP_EDP_BKLTEN Waveform
Change-Id: Icea1e035d62c89ea26bc58afa1d64ab8a448cc04
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88772
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
The alignment for several memory regions in the linker script was
specified using numeric values like `4096` or the hexadecimal `0x1000`.
Replace these values with the more readable `4K` shorthand. This change
improves consistency within the file and has no functional impact on
the generated binary.
TEST=Build and boot google/quenbi.
Change-Id: I28fdf3714d96f5e68a615d1550cf47d975ab5685
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Currently the SSD is preventing the system from entering S0ix sleep,
the system PKG C-State is stuck at PC3.
Intel RDC#642067 reveals while PEG60 is NDA but PEG62 is DA, need to
keep default PEG60 enabled and assign an unused CLKREQ# for port PEG60.
PEG60 is 00:06.0 (CPU PCIe Root port A).
PEG62 is 00:06.2 (CPU PCIe Root port B).
Caboc connectd SSD to PEG62 while PEG60 is not used.
As described above, follow RDC to assign the unused CLKREQ#5 for port
PEG60 and enable its related settings including pcie4_0, GPP_H23 NF2
as SRCCLKREQ#5, vGPIO and confirm the SSD can enter suspend.
BUG=b:435567235
TEST= emerge-brox coreboot
suspend_stress_test pass 100 cycles on SSD sku.
Measured the Boot/Resume time has improved.
seconds_power_on_to_kernel (Boot time)
Before/After 2.616/1.609
seconds_system_resume (Resume time)
Before/After s0ix error/0.338123
Change-Id: I26afeffd466cb2d8e0a0e4213214bde3b0a3b25b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Simon Yang <simon1.yang@intel.com>
The `SSRAM_START/END`, `BSRAM_START/END`, and `AOPSRAM_START/END`
macros were redefined across multiple Qualcomm SoC `memlayout.ld` files.
To reduce code duplication and improve maintainability, this commit
moves these common macros into the shared `<soc/memlayout.h>` header
part of the Qualcomm common code.
The SoC-specific linker scripts are updated to remove the local
definitions.
TEST=Built for all affected SoCs (qcs405, sc7180, sc7280, x1p42100)
Change-Id: I8638b8e03e1e51f57b7e91a072f3d9cdb4ec6200
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88782
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the common Qualcomm SoC include path to the qcs405 Makefile.
This allows the SoC-specific code to use shared headers located in
`src/soc/qualcomm/common/include`, promoting better code reuse and
organization.
TEST=Build for qcs405 target successfully.
Change-Id: Ie4bc9f3a4fc259adcdc4107c92aab0cb5c8676c1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit refactors how the CBMEM top address is determined. Instead
of using a hardcoded value, the CBMEM top address is now starts at
offset `_dram_smem`.
Note: CBMEM region grows from top to bottom hence, starting cbmem_top
at offset `_dram_smem` won't override the SMEM reserved range.
The hardcoded value is problematic as it overrides the SMEM reserved
range and resulted into the boot halt.
The changes include:
- cbmem.c: The cbmem_top_chipset() function is updated to return the
address of the `_dram_smem` linker symbol plus its size.
This refactoring removes a magic number from the code, improving
readability, maintainability, and consistency with how other memory
regions are handled.
BUG=b:437948495
TEST=Able to ensure booting google/quenbi till kernel w/o
abrupt shutdown.
```
[DEBUG] CBMEM:
[DEBUG] IMD: root @ 0xff7ff000 254 entries.
[DEBUG] IMD: root @ 0xff7fec00 62 entries.
```
Change-Id: Idb6a8a47f38d873c6ad4f0d995e77e657cc00ac0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit refactors the DRAM memory layout to reserve additional
regions critical for platform functionality and debugging. It
consolidates several CPUCP-related memory areas and adds new
reservations for Ramdump and Shared Memory.
- Ramdump and Shared Memory: New reserved regions, dram_ramdump and
dram_smem, are added to protect memory used for crash dumps and
inter-processor communication.
- CPUCP Optimization: The individual NCC, CPUCP, and CPUCP-DTS regions
are consolidated into a single, contiguous dram_cpucp region from
0x80A00000 to 0x815A0000. This simplifies the memory map and
optimizes resource allocation.
Reserving these regions is crucial to prevent other bootloader stages
or the kernel from overwriting critical firmware data, which could lead
to unexpected behavior or system instability.
BUG=b:437948495
TEST=Able to ensure booting google/quenbi till kernel.
Change-Id: I80f6d288dd054a34a1e60736c8b14f072559c1ac
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88779
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the x1p42100 platform to support a dynamic memory
layout for DRAM. This is a crucial step toward supporting different
board variants with varying memory capacities.
The changes involve:
- ramstage build: The mmu.c source file is now included in the ramstage
build, providing the necessary functions to configure the Memory
Management Unit (MMU) for fragmented memory regions.
- Linker Script (memlayout.ld): The dram_space_1 and dram_space_2
regions are statically defined with their maximum possible sizes.
- SoC Initialization (soc.c): The soc_read_resources function is
refactored to use a new helper function, qc_get_soc_dram_space_config,
to retrieve a list of available DRAM regions. It then iterates through
this list to dynamically register each memory region with ram_range.
This replaces the previous static ram_range call with a more flexible
approach that can handle fragmented memory maps. Reserved regions are
also updated to use a dynamic index.
This refactoring allows the system to correctly handle memory maps for
devices with more than 2GB of DRAM, which was a limitation of the
previous static configuration.
TEST=Able to build and boot google/quenbi w/ 16GB of DRAM (using
DDR_SPACE and DDR_SPACE_1 regions).
Change-Id: If94644110272713f77db5a0dd6d23ec0798a15f0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88753
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Stating with Qualcomm X1P42100 SoC generation, the DRAM memory map is
not expected to be contiguous (unlike previous generations) therefore,
the memory map could be something like this.
1. Assume hardware design has 4GB of DRAM then the memory map would
look like:
- DDR_SPACE (2 GB) : 0x80000000 - 0x100000000
- DDR_SPACE_1 (2 GB) : 0x880000000 - 0x900000000
2. Assume hardware design has 16GB of DRAM then the memory map would
look like:
- DDR_SPACE (2 GB) : 0x80000000 - 0x100000000
- DDR_SPACE_1 (14 GB) : 0x880000000 - 0x400000000
3. Assume hardware design has 64GB of DRAM then the memory map would
look like:
- DDR_SPACE (2 GB) : 0x80000000 - 0x100000000
- DDR_SPACE_1 (30 GB) : 0x880000000 - 0x1000000000
- DDR_SPACE_2 (32 GB) : 0x8800000000 - 0x9000000000
This commit introduces logic to handle systems with fragmented DRAM
configurations. Previously, the Memory Management Unit (MMU) was
configured assuming a single, contiguous block of DRAM.
This change extends the MMU setup to properly configure multiple,
non-contiguous DRAM regions.
The changes include:
- Declaring dram_space_1 and dram_space_2 as optional regions, allowing
the dynamic allocation for these DRAM ranges based on DRAM capacity of
the platform.
- Introduce `qc_get_soc_dram_space_config` function that takes care of
DRAM based resource splitting as per `_dram`, `_dram_space_1` and
`_dram_space_2` region limit.
- Modifying qc_mmu_dram_config_post_dram_init() to check for these
optional regions and configure them individually. This ensures all
available DRAM is correctly mapped and accessible to the system.
This approach improves flexibility and allows coreboot to support a
wider range of Qualcomm platforms with different memory layouts.
TEST=Able to boot google/quenbi to OS.
Change-Id: If3788f4c77535f9a5e47ad2034ab9a8e0fe85b51
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88752
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes DRAM an explicit region by introducing
DECLARE_OPTIONAL_REGION(dram) and DRAM_END().
Note: many SoC platforms determine DRAM size and layout dynamically
during boot, making a static compile-time value is not feasible always.
Attempting to use REGION_SIZE(dram) in this scenario would result in a
missing symbol `_dram_size` error.
By making dram an optional region, we allow its size and address to be
defined only when available, preventing build failures on platforms
that configure DRAM dynamically.
The old extern u8 _dram[] is removed, as it's now covered by the new
region definition.
This is a preparatory step for future changes that will make use of
the new DRAM_END() macro.
This symbol is necessary for systems that require
the DRAM size to be known and accessible from the linker script or
other parts of the build system.
Additionally, a new macro DRAM_END(addr) is defined in memlayout.h.
This macro provides a consistent way to mark the end of the DRAM
region, similar to how REGION_END and other start/end macros are used
throughout the codebase.
TEST=Able to build and boot google/quenbi.
Change-Id: Ib98ec4b991eed56385c83be6a9ca39ff1380ff1b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit refactors the qc_mmu_dram_config_post_dram_init function
to remove the ddr_base parameter. The function can now retrieve the
base address of the DRAM from the ddr_region global variable, which
is already available.
TEST=Able to build and boot google/quenbi.
Change-Id: I97159dee6a035ed3e38cbfca1e44b8e671d15fc1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch adds support for hardware watchdog event logging which is
useful while debugging crashes or abnormal shutdown.
TEST=Able to build and boot google/bluey.
Change-Id: Iaa60e4eb564a1f517b979c2007707746f3453092
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88775
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Value is from vendor, change to 0x0807 the LED behavior meets spec:
LED0: Green when connected.
LED2: Blink amber when active.
BUG:b=437217680
TEST=emerge-brox coreboot
Check firmware log output
[DEBUG] r8168: Customized LED 0x807
[DEBUG] r8168: read back LED setting as 0x807
Verified the LED behavior of LAN actions meets spec.
Change-Id: I37a3c62b38cd7a3a23b4f8a9c3cb2432393c7a27
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88720
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch enables DDC only for HDMI (Port B) to support EDID/DDC
communication so that the system can communicate with the monitor and
set up the display properly.
Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86
BUG=b: None
TEST= Build Ocelot and verify it compiles without any error.
Change-Id: I6bf7c249dd154ab12a4b2539ecb7872392c132fa
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88648
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While helping with board bringup, I noticed that CRB is enabled in mFIT
but it was missing in board code.
Change-Id: I8f34cac2508ef15f5b6f6542a912fb12af3c2dbf
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: KunYi Chen <kunyi.chen@gmail.com>
dev->path.gicc_v3.mpidr is an unsigned long long, so the format
specifier should be %llx, not %x. Keep the minimum 2 digit output.
BUG=CID 1611971
Change-Id: I126b0281efcba2c3e41cf6da4d006b8d2eb7215b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Generate RAM ID for
IC SDRAM(315P) MT62F1G32D2DS-023 WT:C
IC SDRAM(315P) H58G56CK8BX146
IC SDRAM(315P) K3KL8L80EM-MGCU(FBGA)
DRAM Part Name ID to assign
MT62F1G32D2DS-023 WT:C 7 (0111)
H58G56CK8BX146 7 (0111)
K3KL8L80EM-MGCU 7 (0111)
BUG=b:438402880
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I7ff2f2d43784a6034c1262913dbeaffc1dc3036f
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Counting the entries on the verb table, there are 10 "AZALIA_" macros
and 44 32-bit values. Therefore, the correct amount of entries should be
10 + (44 / 4) = 21.
Change-Id: Ic858d9076d12755014caa28e428d57dde0ef375d
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88645
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch the DRAM_ID 0 memory part from the H58G56BK7BX068 memory part
to H58G56BK8BX068 for ocelot.
BUG=b:437989448
TEST=`emerge-ocelot coreboot chromeos-bootimage', flash and boot
ocelot and verify it's able to train memory without error.
Change-Id: I979a75f770cc5bf82b7c5537e4c36651ecc21ea6
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88759
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Our strsep() function is slightly incorrect in that it leaves the
`stringp` pointer pointing to the terminating NUL byte after parsing the
last token. The man page for official implementations says:
> In case no delimiter was found, the token is taken to be the entire
> string *stringp, and *stringp is made NULL.
This doesn't affect things in practice much because we also
(incorrectly) return NULL when called with `**stringp == '\0'`, meaning
the usual pattern of calling `strsep()` in a row without checking
results first still works when there are less tokens than expected,
since we terminate early from that case instead. But it does break the
edge cases where the caller wants to check if there were extra bytes
beyond the last token (`stringp == NULL`), and where we call `strsep()`
on a pointer pointing directly to a terminating NUL byte already
(supposed to return an empty string but our implementation actually
returns NULL). It doesn't look like these edge cases occur anywhere in
current libpayload or depthcharge code.
This patch fixes the issue and also adds a unit test to ensure it
remains correct in the future. (Also move the definition of the `errno`
variable from lib.c into string.c, because `perror()` in string.c is the
only function that actually needs that, and the crazy linker error you
get when only linking one but not the other into a test will waste you
half an hour to figure out.)
Change-Id: I610b5117710c110bcba4fac2a0bb6c13f4f8d046
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88729
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rearm and clear functions are called only if a valid crashlog is
present and extracted. If there is no valid crashlog, rearming will
lead to incorrect notification and skipping of the next crashlog event
BUG=b: None
TEST= PMC discovery buffer - rearmed status bit (trig_armed_sts)
MMIO read of Bit position 25 is rearmed status bit
MMIO read of desc_table_addr = (bar_address + offset)
desc_table_addr = 0x9c198000 + 0x1d00 = 0x9c199d00
:1 for cold boot and
:0 for warm boot after manual crash
Change-Id: I42da487abd383567d7945835b738557e2e3fa714
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
After crashlog data is extracted, CPU rearm command is issued to
prepare the crash logging mechanism for future events. Instead of
command and response polling of mailbox, watcher interface which is a
direct MMIO based, low latency control register is used for efficiency.
In PTL, a Crashlog watcher providing control the same way provided by
Crashlog Mailbox Interface used by (mainly) BIOS is used for all CPU
crashlog control requests from BIOS to PUNIT.
BUG=b: None
TEST= Manually trigger crash using command
iotools mmio_write32 (baraddress + watcher offset=0x10) 0x20000000
followed by warm boot, check rearm status - which is 25th bit of
*(bar_address)
Change-Id: I89dd23fad144c1c7122b5536f1ac848ea66ea6b1
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Set I2C2, I2C3, and I2C4 controllers to disabled in serial_io_i2c_mode
Remove configuration for I2C2, I2C3, and I2C4 from common_soc_config
Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86
BUG=b: None
TEST= Build Ocelot and verify it compiles without any error.
Change-Id: Ibe26bde3ffbd4b188584369cdd686ffb116d6a7d
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88650
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
According to MediaTek, this delay was added in the driver bring-up stage
to mitigate the display garbage issue. Now, the delay can be removed.
BUG=b:434574691
TEST=Check FW screen on Navi
Change-Id: I5408d95be7a4aaf8bb4bb639c319320514c4fd99
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88744
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Meaure the execution time for following eDP functions.
- dptx_check_sinkcap
- dptx_get_edid
- dptx_set_trainingstart
- mtk_edp_init
These dptx_* functions are the primary contributors to the execution
time of mtk_edp_init, which is only called in dev/recovery mode. This
insight can be used for future boot time optimization by breaking down
the eDP initialization process.
TEST=Boot with DEV mode using the boot image without serial console
support.
TEST=cbmem -c|grep "done after"
[INFO ] dptx_check_sinkcap done after 38 msecs
[INFO ] dptx_get_edid done after 294 msecs
[INFO ] dptx_set_trainingstart done after 100 msecs
[INFO ] mtk_edp_init done after 438 msecs
Change-Id: I7aabf3a33b9628f20fe16980033b00de9afc44e6
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
