Convert all PCI device and USB port references in the reef devicetrees
to use aliases from the Apollolake chipset.cb instead of direct device/
function numbers. This improves maintainability by using symbolic
names, and reduces file size by eliminating entries which match those
in the chipset devicetree.
TEST=Build all reef variants
Change-Id: I08f96d2367fa8fc1ac7eb785c0d5cc08e293921b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90927
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Convert all PCI device and USB port references in octopus baseboard
devicetree and variant overridetrees to use aliases from the Geminilake
chipset.cb instead of direct device/function numbers. This improves
maintainability by using symbolic names, and reduces file size by
eliminating entries which match those in the chipset or baseboard
devicetrees.
TEST=Build all octopus variants
Change-Id: Ic4f93608234b52d548d8e5f94b137754e8924484
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
It's selected at the SoC level now, so no need for the mainboard to
select it as well.
TEST=build octopus
Change-Id: Id8bf73de73fd9c93e875c52b339b63970c32d50a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add USB port aliases to chipset_glk.cb and chipset_apl.cb to enable
boards to use device ref syntax for USB devices. Port counts match
hardware specs: GLK has 9 USB2/7 USB3 ports, APL has 8 USB2/7 USB3
ports.
Select 'DRIVERS_USB_ACPI' so that the required USB ACPI drivers are
built and linked for all boards.
Change-Id: Ibc7dd2cbfda8c8eb42b243ea7adcdb6d1fdea98b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Select SOC_INTEL_COMMON_BLOCK_ASPM and use the SoC common code for
programming PCIe root port power management. This adds programming of
PCIe RP clock PM and port speed, as well as allows for user override
via setup options for all fields. Remove the now-unused static methods
get_l1_substate_control() and get_aspm_control().
Additionally, check the port enable status before declaring the root
port config struct, to be consistent with ADL and MTL.
Change-Id: Ic30d714e609612ea46d34252c7c1d799652a9c2b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90879
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move SDXC device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from sd.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
SDXC controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: Ifee16988d0e5625a7b3c2be51ab70d2c8471747a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Move CNVI WiFi device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them.
Remove corresponding DIDs from cnvi.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
Remove the static declaration from cnvi_wifi_ops so the symbol is
exported and visible outside of cnvi.c.
This standardizes the approach across Intel SoCs and makes the
CNVI WiFi controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: I82a2b20a8b967d1a3d5a80ae477def260c366be7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90922
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move XDCI device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from xdci.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
XDCI controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: Ie8f8b5a952d072ecd1721bc8537734e85769b09d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Move XHCI device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from xhci.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
XHCI controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: I4a0551a0fc5a233153c62d5bb7b0b2f3596a81ac
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Move HDA device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from hda.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
Add 'Select SOC_INTEL_COMMON_BLOCK_HDA` to Apollolake/Geminilake
so those platforms can make use of the common driver. Since no
APL/GLK boards currently select `SOC_INTEL_COMMON_BLOCK_HDA_VERB`
the addition is a no-op.
This standardizes the approach across Intel SoCs and makes the
HDA controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common HDA driver code.
Change-Id: I0b3af4c2a441d4897341ee6c2cc5d75d70a6ebc4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90919
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move SMBUS device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from smbus.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
SMBUS controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: I1c742836d923eb8f521bdbd7fa8260c82c1156ac
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Move GSPI/SPI device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from spi.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
GSPI/SPI controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: Ia379cff36a5b277d89cad757edc094a5d786a51b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90917
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move UART device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from uart.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
UART controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: Id26dad7997d64bcaad53fa39be23e52cb47dcc1d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90916
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move SATA device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from sata.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
Add `select SOC_INTEL_COMMON_BLOCK_SATA` to Apollolake SoC so that
the common block code is included, which it was not previously, even
though the APL/GLK PCI DIDs were included in the list. The net
effect is that the `SATA` ACPI device is now added to SSDT for
APL/GLK boards when they have SATA enabled.
This standardizes the approach across Intel SoCs and makes the
SATA controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: I4c296a88c4da5f91d1039877ec858857496527f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Move I2C device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from i2c.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
I2C controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common I2C driver code.
Change-Id: Ib68dd19c7c94d4cb6b41a1caf092b77f463c1c74
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90906
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
CFR default overrides use SM_OBJ_* kinds, but
write_numeric_option() compared them to CFR_TAG_OPTION_*,
so enum/number/bool overrides were always skipped.
Compare kinds against the expected SM_OBJ_* for each numeric
tag, then apply the override.
Change-Id: I02046974a7b0a3ef32973689833e1b0d38a5d6f4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90911
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move PCIe root port operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from pcie.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files. Some of these
will be removed/cleaned up in subsequent patches.
This standardizes the approach across Intel SoCs and makes the
PCIe root port configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common PCIe driver code.
Change-Id: I8586b6efb8dbe164bc2a1d68b7131ffa22b00001
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Convert all PCI device and USB port references in the librem_jsl
devicetree to use device aliases from the Jasperlake chipset.cb instead
of direct device/function numbers. This improves maintainability by
using symbolic names, and reduces file size by eliminating entries
which match those in the chipset devicetree.
Additionally, the p2sb device reference is dropped, as the correct state
(hidden) is set by the chipset devicetree.
TEST=Build librem_jsl
Change-Id: Iba2959156ccede68bceb46f8458676bc7a88247a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90903
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board was missing the control of Bluetooth; add it so it
matches all the other Star Labs boards.
Change-Id: I11e39b4c02095b762717ff041a654838fd4c5897
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90958
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board used the older "wireless" option, which no longer exists to
control wireless. Update it to check "wifi".
Change-Id: I8ddec94ea729790c9d13cd54516b8802df0e77aa
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90957
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Convert all PCI device and USB port references in the jasperlake_rvp
devicetree to use device aliases from the Jasperlake chipset.cb instead
of direct device/function numbers. This improves maintainability by
using symbolic names, and reduces file size by eliminating entries
which match those in the chipset devicetree.
Additionally, the p2sb device reference is dropped, as the correct state
(hidden) is set by the chipset devicetree.
TEST=Build jslrvp
Change-Id: I04fd2d1655f08fb0671deeeb55a3e88eb97b7f44
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90902
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CRET uses CNVi WiFi, not discrete, and has nothing attached to this
port, so don't enable it.
TEST=build/boot CRET
Change-Id: Iac9e01c6ecd4f3f32cd1c39a87a10530a36b40a4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90901
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Convert all PCI device and USB port references in dedede baseboard
devicetree and variant overridetrees to use aliases from the Jasperlake
chipset.cb instead of direct device/function numbers. This improves
maintainability by using symbolic names, and reduces file size by
eliminating entries which match those in the chipset or baseboard
devicetrees.
TEST=Build all dedede variants
Change-Id: I00c8f79ab040cd634ea94d4d596128ef3d6f7e73
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Similar to other Intel SoCs, create a chipset.cb for Jasperlake
giving alias names to all known PCI devices. Taken from comments in
existing JSL board devicetrees, cross-referenced against the publicly
available JSL EDS.
At the same time, remove the usb2_lte device aliases in the BOTEN and
DRAWCIA dedede variants, and replace their references with the new
usb2_port4 alias, since we can only have a single alias per device.
TEST=build boten and drawcia dedede variants
Change-Id: I32552dbe0ab5305ea44b5e89432603884cf6589f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Commit ad6e3c847f ("tree: Drop Intel Ice Lake support") removed most
of the Ice Lake PCI IDs, but missed the ones with the ICP prefix
(Ice Point? Ice Lake Point?). Remove all PCI_DID_INTEL_ICP* defines
and references in common block drivers.
Change-Id: I9d33c69d174130aa781a00441fca367e0a67bcb4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90904
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
I checked with the EE team. The previous status was neither D3hot
nor D3cold; it was in idle state, with power consumption around 1W.
With the locally tested BIOS that includes this change, the system
now enters D3hot and the power consumption is reduced to about 0.4W,
achieving the power-saving goal.
BUG=b:475990377
BRANCH=none
TEST=Build and boot to OS, check the code change could obtain
power saving.
Change-Id: Ib407e68dc70509e4431d87993597cd096dc0d9bc
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90907
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Turin OpenSIL driver and submodule pointing to turin_poc branch
of github.com/openSIL/openSIL repository.
Change-Id: Idd6d4e78a055926061de330da620c943b42a50a7
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Program ASPM on PCIe root ports when no endpoint device is connected
at boot. This ensures proper power management for TBT ports that often
do not have devices connected at boot.
Add pciexp_enable_aspm_root_port_only() to program ASPM based on the
root port's Link Capabilities, and call it from pciexp_scan_bus() when
no children are detected on a root port.
TEST=build/boot Starlabs Starfighter MTL, verify ASPM enabled on TBT
ports even when no devices attached via lspci:
LnkCtrl: ASPM L1 Enabled
Change-Id: I1da6d36afcbe18411c01ceabf8b903c4ae13cd73
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
All variants which use a discrete (vs CNVi) WiFi module enable
RP8 (or RP7) in their overridetree, so enabling RP8 in the baseboard
is superfluous. Additionally, disabling it in the baseboard makes
things cleaner when switching to using chipset devicetree references
in a subsequent patch.
Change-Id: I591508e5c41f2019a6360e08c89b0a4982178a07
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
In order to keep coreboot and FSP in sync for which i2c ports are
enabled, disable all I2C ports in the baseboard, in both the PCI
devices and the SerialIoI2cMode register. Each variant enables only the
ports it uses by overriding the SerialIoI2cMode register index for
those ports, and enabling the PCI device(s) and defining the attached
devices. References to i2c ports which were off/disabled are removed
from all variants, as they are redundant.
TEST=build google/dedede (dexi), verify SerialIoI2cMode in static.c
enables only the single port used (i2c4)
Change-Id: I7fcab382cc0eaf4fb0bc9d8095587018b4e226b1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
The alias isn't referenced anywhere, so remove it in preparation of
adding a chipset devicetree using the same alias in a subsequent patch.
TEST=build google/dedede (dexi)
Change-Id: I0745eab9b0947b790f64383549e205bd906ba555
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90896
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add RAM ID for K3KL8L80CM-MGCT. And importing a single RAM device,
so use mb_get_channel_disable_mask to distinguish it.
BUG=b/468889066
BRANCH=None
TEST=boot to kernel success, and the log shows that the RAM ID is correct.
Change-Id: Idc1e890ab826ec008031f54e0fc445fa5ee62978
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This change adds support for I2S codec in the device tree and enables
it based on the fw_config based on WCL_GPIO_Implementation Rev0p7.
RDC Doc no: 836031
BUG=b:465888555
TEST=Boot on google ocelot board and Enable I2C Codec for Audio.
Check Mic and Speaker functionality
Change-Id: I51fb849bf365108be1ff59d65069329e5fd08824
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90427
Reviewed-by: P, Usha <usha.p@intel.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Checked with the SED team and confirmed that the HID name needs
to be changed to "GT 7936".
BUG=b:478990702
BRANCH=none
TEST=Build the image and boot to the OS, then check that
the touchscreen HID name has changed to "GT 7936"
in the diagnostics app.
Change-Id: Id0ce797b121c4a7bcf7bf15bfc81e9b079ebb3c4
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90941
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
TEST=Boot glinda based mainboard and see Type 19 and 20 entries using
dmidecode tool.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9a0abab9a5324f83659180a3842a8b5d9c6b3820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The current CBMEM top is situated at the base of 'dram_xbl_log'
(0x81A00000), leaving only 4.4MB of usable memory below it. This
space has become insufficient for the growing size requirements of
the coreboot configuration tables and boot services.
Relocate the CBMEM top to the base of the PIL region (0x866C0000).
This move increases the available contiguous memory for CBMEM
allocation from 4.4MB to 7.3MB, ensuring sufficient headroom for
the tables and reducing fragmentation for the OS and runtime services.
Changes:
- Update cbmem_top_chipset() to return _dram_pil as the new boundary.
- Update memlayout.ld documentation to reflect CBMEM's new position
directly below the PIL region.
TEST=Verified CBMEM initialization on Bluey; confirmed coreboot
tables are correctly allocated at the new high-memory boundary and
no overlaps occur with reserved regions.
Change-Id: I26d95b952634ce06ed2171c75bc6a129c15ec3b8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90912
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
The previous 12MB WP_RO size is an invalid range for the SPI controller.
Hardware write-protection requires power-of-two or specific
block-aligned boundaries, making 12MB unenforceable.
Reduce WP_RO to 8MB to ensure hardware WP can be correctly enabled.
The reclaimed space is assigned to RW_UNUSED.
BUG=b:479139462
TEST=Build and verify FMAP layout on Bluey; confirm hardware WP
enforcement.
Change-Id: I4515eab3941913942fc5994e7094986e2edbd6d6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90952
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit c4be70f6ff.
Reason for revert: The CL caused a hang in Depthcharge on
Google/Quartz.
BUG=b:479143030
TEST=Verify boot on Google/Quartz.
Change-Id: I38087d0b2dd218dfb32a02c343b199708bb47d49
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In some use cases, we want to add items to the linked list and then
iterate over them with the insertion order. With the current API, the
call site needs to either use the inefficient list_append() function to
append items to the end of the list, or manually maintain a "tail"
node pointer.
To support that use case and make the change backward compatible, add a
helper list_init() function to initialize the list as a circular linked
list. list_init() is automatically called within list_insert_after() and
list_append(). In list_insert_before(), an assertion is added to avoid
an insertion before the head node (which should be invalid). The
implementation ensures that the list is initialized as a circular one
whenever the first element is added. That also allows all call sites to
be auto-upgraded to the "circular list" implementation without any
modification.
Modify list_for_each() to support circular lists, and improve
list_append() efficiency by inserting the new node before the
placeholder head node. Also add a few assertions in the implementation.
Add a new test case to test iterating over an empty list.
Note that '(uintptr_t)ptr + (uintptr_t)offsetof(typeof(*(ptr)), member)'
was used instead of the simpler '&((ptr)->member)' because GCC9+ assumes
that the address can never be NULL. See commit 88991caf00
("include/list.h: Add support for GCC9+) for details. Now, with the
new list_for_each() implementation, that pointer value can never be
NULL.
Change-Id: I8451f711d4e522e239c241b3943e00070896dec9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90799
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the 4K alignment for PRERAM_DMA_COHERENT and adjust the post-RAM
memory layout to ensure page-aligned boundaries.
- Shift PRERAM_DMA_COHERENT from 0x14857000 to 0x14858000. This 4K
alignment is required for the MMU to correctly apply uncached
attributes without overlapping adjacent regions.
- Increase POSTRAM_STACK from 16K to 32K to provide more headroom
for complex ramstage operations.
- Shift and expand POSTRAM_DMA_COHERENT to 0x8000C000 (16K). This
ensures the coherent region starts on a 4K boundary after the
expanded stack, preventing cache coherency issues.
This alignment fix resolves intermittent SPI DMA failures and hash
mismatches observed when the DMA engine was handed unaligned
buffer addresses.
BUG=b:477842629
TEST=Verified successful boot on Bluey; confirmed SPI read
stability and vboot verification pass.
Change-Id: Ic5f813e4722d732c122186897abf845e4060db37
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90888
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boost the SPI bus clock frequency from 50MHz to 75MHz in the
bootblock early initialization.
This increase reduces the latency for loading subsequent stages
(romstage/ramstage) from the SPI flash. Since the QSPI core
can now be configured to 300MHz, this 75MHz bus speed
maintains a stable 1:4 integer divider ratio, ensuring optimal
signal integrity and timing margins for the flash interface.
BUG=b:478226455
TEST=Verified successful boot on Bluey. Observed a reduction (10ms)
in 'read SPI' duration in the console logs and confirmed that the
vboot hash verification passes consistently.
Change-Id: Idea0dbdd435cbbfe22a756d2b94b1cdfa3c70ffe
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Add a new frequency entry to the QSPI core clock configuration table
to support 75MHz (75 * 4 = 300MHz).
This is achieved by using the GPLL0 600MHz source with a divisor of 2.
Providing a 300MHz core clock allows for more granular control over
the physical bus speed (SCK). Specifically, it enables a stable 75MHz
SPI bus frequency via a clean 1/4 divider, which is an optimization
target for improving boot times on Bluey/Quenbi platforms.
BUG=b:478226455
TEST=Verified that 'clock_configure_qspi' can correctly look up and
set the 300MHz frequency in romstage.
Change-Id: I5320a68ff50a0d79daa2fc855b18b0f3ae819bbe
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90886
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
With the current implementation of assert() for ENV_TEST, the printk()
function must be linked. As we are already using cmocka's mock_assert()
implementation for unit tests, those printk() calls within
assert-related macros should be changed to no-ops.
Also, disable __build_time_assert() for ENV_TEST.
Change-Id: Ia9bea29a32362d68dff89bb7bbf417126ac31fb7
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90870
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For both x86 and non-x86 its the same anyway, so factor it out.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I30e6d1da8a663cd79d59d55446eda2b70269f118
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Its actually the size FMAP flash region so the name is more appropriate.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I152b66abedb68f1ab809d918502efe096e9dde59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90811
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some SSDs connected to the PCH-attached PCIe root port/m.2 socket need
a small delay in order to be reliably detected. Add a 15ms delay (the
default is 0) to ensure this.
TEST=build/boot Starfighter MTL 125H/285H with Samsung 970 EVO plus,
WD SN720, and Intel Optane P1600x SSDs in outer SSD socket. Ensure
all drives detected and bootable after both cold and warm resets.
Change-Id: I16ec0a313fc7cccb2807593c07db04cdbb59c979
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90880
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Properly advertise I/O ports decoded by H8 and PMH7. Therefore
implement read_resources() and set_resources() in coreboot and
advertise the ports using ACPI.
TEST=I/O ports are properly seen as fixed and assigned in
coreboot and the OS.
Change-Id: Iae1b72d2d565750020f2943804165b9d5d2efdfb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90723
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When APM_CNT_ACPI_DISABLE is issued during LPC init it will
enable SMI's when the EC asserts the GPE_EC_SCI GPIO, looking like:
[NOTE ] coreboot-25.12 x86_64 smm starting (log level: 6)...
[DEBUG] GPI (mask 0002)
This happens on all ec_read() calls whenever bits in the status
register change, causing lots of unnecessary SMIs at boot.
Cache the EC version string when it's first read and use the
cached version when writing SMBIOS tables.
While on it introduce defines for registers and drop function
from global scope.
TEST=Seen less SMIs during boot. Version string is still correctly
shown in dmidecode.
Change-Id: I514c628947c4e14f2379f7e2f265f28a9c7086d6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
