util/inteltool: improve support for Comet Lake-U/H
Add support for MCH, spi and bios_cntrl, LPC/eSPI, GPIO, EPBAR, DMIBAR and add product description. References: * 10th Generation Intel® Core™ Processors, Datasheet Volume 1 of 2 * 10th Generation Intel® Core™ Processors, Datasheet Volume 2 of 2 * Intel® 400 Series Chipset Family Platform Controller Hub, Datasheet Volume 1 of 2 * Intel® 400 Series Chipset Family Platform Controller Hub, Datasheet Volume 2 of 2 Change-Id: I9ae2447d2f122b9c05bcd50c16c1f19330ee9656 Signed-off-by: Vladimir Epifantsev <volatilefield@outlook.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Vladimir Epifantsev
Matt DeVillier
parent
a2a868f199
commit
7ce04e9291
10 changed files with 190 additions and 15 deletions
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@ -1118,6 +1118,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
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case PCI_DEVICE_ID_INTEL_B760:
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case PCI_DEVICE_ID_INTEL_HM770:
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case PCI_DEVICE_ID_INTEL_WM790:
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case PCI_DEVICE_ID_INTEL_HM470:
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case PCI_DEVICE_ID_INTEL_C262:
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case PCI_DEVICE_ID_INTEL_C266:
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case PCI_DEVICE_ID_INTEL_ADL_P:
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@ -186,6 +186,7 @@ const struct gpio_community *const *get_gpio_communities(struct pci_dev *const s
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case PCI_DEVICE_ID_INTEL_QM370:
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case PCI_DEVICE_ID_INTEL_HM370:
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case PCI_DEVICE_ID_INTEL_CM246:
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case PCI_DEVICE_ID_INTEL_HM470:
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*community_count = ARRAY_SIZE(cannonlake_pch_h_communities);
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*pad_stepping = 16;
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return cannonlake_pch_h_communities;
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@ -145,11 +145,17 @@ static const struct {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U,
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"10th generation (Icelake family) Core Processor (Mobile)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_U1,
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"10th generation (Comet Lake family) Core Processor (Mobile)" },
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"10th generation (Comet Lake-U family) Core Processor (Mobile)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_U2,
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"10th generation (Comet Lake family) Core Processor (Mobile)" },
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"10th generation (Comet Lake-U family) Core Processor (Mobile)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_U3,
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"10th generation (Comet Lake family) Core Processor (Mobile)" },
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"10th generation (Comet Lake-U family) Core Processor (Mobile)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2,
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"10th generation (Comet Lake-H family) Core Processor (Mobile)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2,
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"10th generation (Comet Lake-H family) Core Processor (Mobile)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2,
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"10th generation (Comet Lake-H family) Core Processor (Mobile)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HEWITTLAKE,
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"Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D (Hewitt Lake)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SAPPHIRERAPIDS_SP,
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@ -435,6 +441,7 @@ static const struct {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK_LPC, "Gemini Lake" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H510, "H510" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H570, "H570" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM470, "HM470" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z590, "Z590" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q570, "Q570" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B560, "B560" },
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@ -617,6 +624,22 @@ static const struct {
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"Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2,
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"Intel(R) UHD Graphics for 11th Gen Intel(R) Processors" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT1_S_1,
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"Intel(R) CometLake-S GT1" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT1_S_2,
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"Intel(R) CometLake-S GT1" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT2_S_G0,
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"Intel(R) CometLake-S GT2" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT2_S_P0,
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"Intel(R) CometLake-S GT2" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT1_H_1,
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"Intel(R) CometLake-H GT1" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT1_H_2,
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"Intel(R) CometLake-H GT1" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT2_H_R0,
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"Intel(R) CometLake-H GT2" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CML_GT2_H_R1,
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"Intel(R) CometLake-H GT2" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_S_GT1,
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"Intel(R) AlderLake-S GT1" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_S_GT1_2,
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@ -224,6 +224,7 @@ static inline uint32_t inl(unsigned port)
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#define PCI_DEVICE_ID_INTEL_WM590 0x4389
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#define PCI_DEVICE_ID_INTEL_QM580 0x438a
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#define PCI_DEVICE_ID_INTEL_HM570 0x438b
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#define PCI_DEVICE_ID_INTEL_HM470 0x068d
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#define PCI_DEVICE_ID_INTEL_C252 0x438c
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#define PCI_DEVICE_ID_INTEL_C256 0x438d
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#define PCI_DEVICE_ID_INTEL_W580 0x438f
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@ -399,6 +400,9 @@ static inline uint32_t inl(unsigned port)
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#define PCI_DEVICE_ID_INTEL_CORE_CML_U1 0x9b51 /* Cometlake U (Mobile) */
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#define PCI_DEVICE_ID_INTEL_CORE_CML_U2 0x9b61 /* Cometlake U (Mobile) */
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#define PCI_DEVICE_ID_INTEL_CORE_CML_U3 0x9b71 /* Cometlake U (Mobile) */
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#define PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2 0x9b44 /* Cometlake H 8+2 (Mobile) */
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#define PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2 0x9b54 /* Cometlake H 6+2 (Mobile) */
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#define PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2 0x9b64 /* Cometlake H 4+2 (Mobile) */
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#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_2 0x9a04 /* Tigerlake UP3 2 Cores */
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#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_U_4 0x9a14 /* Tigerlake UP3 4 Cores */
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#define PCI_DEVICE_ID_INTEL_CORE_TGL_ID_Y_2 0x9a02 /* Tigerlake UP4 2 Cores */
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@ -506,6 +510,14 @@ static inline uint32_t inl(unsigned port)
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#define PCI_DEVICE_ID_INTEL_TGL_GT1_2 0x9A68
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#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_1 0x9A78
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#define PCI_DEVICE_ID_INTEL_TGL_GT2_ULT_2 0x9A70
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#define PCI_DEVICE_ID_INTEL_CML_GT1_S_1 0x9BA5
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#define PCI_DEVICE_ID_INTEL_CML_GT1_S_2 0x9BA8
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#define PCI_DEVICE_ID_INTEL_CML_GT2_S_G0 0x9BC8
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#define PCI_DEVICE_ID_INTEL_CML_GT2_S_P0 0x9BC5
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#define PCI_DEVICE_ID_INTEL_CML_GT1_H_1 0x9BA4
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#define PCI_DEVICE_ID_INTEL_CML_GT1_H_2 0x9BA2
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#define PCI_DEVICE_ID_INTEL_CML_GT2_H_R0 0x9BC2
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#define PCI_DEVICE_ID_INTEL_CML_GT2_H_R1 0x9BC4
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/* Elkhart Lake */
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#define PCI_DEVICE_ID_INTEL_EHL_GT1_1 0x4541
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#define PCI_DEVICE_ID_INTEL_EHL_GT1_2 0x4551
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@ -150,6 +150,23 @@ int print_lpc(struct pci_dev *sb, struct pci_access *pacc)
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cfg_registers_size = ARRAY_SIZE(sunrise_lpc_cfg_registers);
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}
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break;
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case PCI_DEVICE_ID_INTEL_HM470:
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dev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 0);
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if (!dev) {
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printf("LPC/eSPI interface not found.\n");
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return 1;
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}
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bc = pci_read_long(dev, SUNRISE_LPC_BC);
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if (bc & (1 << 2)) {
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printf("Device 0:1f.0 is eSPI (BC.LPC_ESPI=1)\n\n");
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cfg_registers = alderlake_espi_cfg_registers;
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cfg_registers_size = ARRAY_SIZE(alderlake_espi_cfg_registers);
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} else {
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printf("Device 0:1f.0 is LPC (BC.LPC_ESPI=0)\n\n");
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cfg_registers = sunrise_lpc_cfg_registers;
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cfg_registers_size = ARRAY_SIZE(sunrise_lpc_cfg_registers);
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}
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break;
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case PCI_DEVICE_ID_INTEL_ADL_N:
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dev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 0);
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if (!dev) {
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@ -229,6 +229,9 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s
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case PCI_DEVICE_ID_INTEL_CORE_CML_U1:
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case PCI_DEVICE_ID_INTEL_CORE_CML_U2:
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case PCI_DEVICE_ID_INTEL_CORE_CML_U3:
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case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2:
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case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2:
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case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2:
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mchbar_phys = pci_read_long(nb, 0x48);
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */
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@ -227,6 +227,35 @@ static const io_register_t alderlake_dmi_registers[] = {
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{ 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask
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};
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/* 10th Generation Intel® Core™ Processors, Datasheet Volume 2 of 2, ID 615211 */
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static const io_register_t cometlake_dmi_registers[] = {
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{ 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability
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{ 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1
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{ 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2
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{ 0x0C, 2, "DMIPVCCTL" }, // DMI Port VC Control
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{ 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability
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{ 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control
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{ 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status
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{ 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability
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{ 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control
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{ 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status
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{ 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability
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{ 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control
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{ 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status
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{ 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration
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{ 0x44, 4, "DMIESD" }, // DMI Element Self Description
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{ 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description
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{ 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address
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{ 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address
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{ 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description
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{ 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address
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{ 0x84, 4, "LCAP" }, // Link Capabilities
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{ 0x88, 2, "LCTL" }, // Link Control
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{ 0x8A, 2, "LSTS" }, // DMI Link Status
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{ 0x98, 2, "LCTL2" }, // Link Control 2
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{ 0x9A, 2, "LSTS2" }, // Link Status 2
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};
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/*
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* Egress Port Root Complex MMIO configuration space
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*/
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@ -292,6 +321,12 @@ int print_epbar(struct pci_dev *nb)
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case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8:
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case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4:
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case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1:
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case PCI_DEVICE_ID_INTEL_CORE_CML_U1:
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case PCI_DEVICE_ID_INTEL_CORE_CML_U2:
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case PCI_DEVICE_ID_INTEL_CORE_CML_U3:
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case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2:
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case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2:
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case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2:
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epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
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epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
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break;
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@ -433,6 +468,18 @@ int print_dmibar(struct pci_dev *nb)
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dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
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dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
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break;
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case PCI_DEVICE_ID_INTEL_CORE_CML_U1:
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case PCI_DEVICE_ID_INTEL_CORE_CML_U2:
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case PCI_DEVICE_ID_INTEL_CORE_CML_U3:
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case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2:
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case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2:
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case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2:
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dmi_registers = cometlake_dmi_registers;
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size = ARRAY_SIZE(cometlake_dmi_registers);
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dmibar_phys = pci_read_long(nb, 0x68);
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dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
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dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
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break;
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case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8:
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case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4:
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case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1:
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@ -555,6 +602,12 @@ int print_pciexbar(struct pci_dev *nb)
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case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_8:
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case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4:
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case PCI_DEVICE_ID_INTEL_CORE_ADL_ID_N_0_4_1:
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case PCI_DEVICE_ID_INTEL_CORE_CML_U1:
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case PCI_DEVICE_ID_INTEL_CORE_CML_U2:
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case PCI_DEVICE_ID_INTEL_CORE_CML_U3:
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case PCI_DEVICE_ID_INTEL_CORE_CML_H_8_2:
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case PCI_DEVICE_ID_INTEL_CORE_CML_H_6_2:
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case PCI_DEVICE_ID_INTEL_CORE_CML_H_4_2:
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pciexbar_reg = pci_read_long(nb, 0x60);
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pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
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break;
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@ -141,6 +141,7 @@ void pcr_init(struct pci_dev *const sb)
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case PCI_DEVICE_ID_INTEL_C252:
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case PCI_DEVICE_ID_INTEL_C256:
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case PCI_DEVICE_ID_INTEL_W580:
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case PCI_DEVICE_ID_INTEL_HM470:
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case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM:
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case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_PREM:
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case PCI_DEVICE_ID_INTEL_COMETPOINT_LP_U_BASE:
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@ -125,6 +125,7 @@ int print_rcba(struct pci_dev *sb)
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case PCI_DEVICE_ID_INTEL_ICH4M:
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case PCI_DEVICE_ID_INTEL_ICH5:
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case PCI_DEVICE_ID_INTEL_ADL_N:
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case PCI_DEVICE_ID_INTEL_HM470:
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printf("This southbridge does not have RCBA.\n");
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return 1;
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default:
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@ -171,6 +171,53 @@ static const io_register_t elkhart_spi_bar_registers[] = {
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{ 0x198, 4, "CSXE_WPR0 - Write Protected Range 0" },
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};
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/* Intel® 400 Series Chipset Family Platform Controller Hub, 620855-002 */
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static const io_register_t cometlake_spi_bar_registers[] = {
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{ 0x00, 4, "BFPREG - BIOS Flash Primary Region" },
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{ 0x04, 2, "HSFSTS - Hardware Sequencing Flash Status" },
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{ 0x06, 2, "HSFCTL - Hardware Sequencing Flash Control" },
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{ 0x08, 4, "FADDR - Flash Address" },
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{ 0x0c, 4, "DLOCK - Discrete Lock Bits" },
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{ 0x10, 4, "FDATA0 - Flash Data 0" },
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{ 0x14, 4, "FDATA1 - Flash Data 1" },
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{ 0x18, 4, "FDATA2 - Flash Data 2" },
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{ 0x1c, 4, "FDATA3 - Flash Data 3" },
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{ 0x20, 4, "FDATA4 - Flash Data 4" },
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{ 0x24, 4, "FDATA5 - Flash Data 5" },
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{ 0x28, 4, "FDATA6 - Flash Data 6" },
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{ 0x2c, 4, "FDATA7 - Flash Data 7" },
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{ 0x30, 4, "FDATA8 - Flash Data 8" },
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{ 0x34, 4, "FDATA9 - Flash Data 9" },
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{ 0x38, 4, "FDATA10 - Flash Data 10" },
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{ 0x3c, 4, "FDATA11 - Flash Data 11" },
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{ 0x40, 4, "FDATA12 - Flash Data 12" },
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{ 0x44, 4, "FDATA13 - Flash Data 13" },
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{ 0x48, 4, "FDATA14 - Flash Data 14" },
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{ 0x4c, 4, "FDATA15 - Flash Data 15" },
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{ 0x50, 4, "FRACC - Flash Region Access Permissions" },
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{ 0x54, 4, "FREG0 - Flash Region 0" },
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{ 0x58, 4, "FREG1 - Flash Region 1" },
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{ 0x5c, 4, "FREG2 - Flash Region 2" },
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{ 0x60, 4, "FREG3 - Flash Region 3" },
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{ 0x64, 4, "FREG4 - Flash Region 4" },
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{ 0x68, 4, "FREG5 - Flash Region 5" },
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{ 0x84, 4, "FPR0 - Flash Protected Range 0" },
|
||||
{ 0x88, 4, "FPR1 - Flash Protected Range 1" },
|
||||
{ 0x8c, 4, "FPR2 - Flash Protected Range 2" },
|
||||
{ 0x90, 4, "FPR3 - Flash Protected Range 3" },
|
||||
{ 0x94, 4, "FPR4 - Flash Protected Range 4" },
|
||||
{ 0x98, 4, "GPR0 - Global Protected Range 0" },
|
||||
{ 0xb0, 4, "SFRACC - Secondary Flash Region Access Permissions" },
|
||||
{ 0xb4, 4, "FDOC - Flash Descriptor Observability Control" },
|
||||
{ 0xb8, 4, "FDOD - Flash Descriptor Observability Data" },
|
||||
{ 0xc0, 4, "AFC - Additional Flash Control" },
|
||||
{ 0xc4, 4, "SFDP0_VSCC0 - Vendor Specific Component Capabilities for Component 0" },
|
||||
{ 0xc8, 4, "SFDP1_VSCC1 - Vendor Specific Component Capabilities for Component 1" },
|
||||
{ 0xcc, 4, "PTINX - Parameter Table Index" },
|
||||
{ 0xd0, 4, "PTDATA - Parameter Table Data" },
|
||||
{ 0xd4, 4, "SBRS - SPI Bus Requester Status" },
|
||||
};
|
||||
|
||||
static int print_bioscntl(struct pci_dev *sb)
|
||||
{
|
||||
int i, size = 0;
|
||||
|
|
@ -303,6 +350,7 @@ static int print_bioscntl(struct pci_dev *sb)
|
|||
size = ARRAY_SIZE(pch_bios_cntl_registers);
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_ADL_N:
|
||||
case PCI_DEVICE_ID_INTEL_HM470:
|
||||
bios_cntl = pci_read_byte(sb, 0xdc);
|
||||
bios_cntl_register = adl_pch_bios_cntl_registers;
|
||||
size = ARRAY_SIZE(adl_pch_bios_cntl_registers);
|
||||
|
|
@ -330,13 +378,29 @@ static int print_bioscntl(struct pci_dev *sb)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int get_espibar_phys(struct pci_dev *sb, struct pci_access *pacc, uint8_t func, uint8_t offset, uint32_t mask, uint32_t *addr) {
|
||||
struct pci_dev *spidev;
|
||||
|
||||
if (!(spidev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, func))) {
|
||||
fprintf(stderr, "Error: no spi device 0:31.%x\n", func);
|
||||
return 1;
|
||||
}
|
||||
|
||||
*addr = pci_read_long(spidev, offset) & mask;
|
||||
if (!*addr) {
|
||||
fprintf(stderr, "Error: no valid bar 0 of device 0:31.%x found %x\n", func, *addr);
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int print_spibar(struct pci_dev *sb, struct pci_access *pacc) {
|
||||
int i, size = 0, rcba_size = 0x4000;
|
||||
volatile uint8_t *rcba;
|
||||
uint32_t rcba_phys;
|
||||
const io_register_t *spi_register = NULL;
|
||||
uint32_t spibaroffset;
|
||||
struct pci_dev *spidev;
|
||||
|
||||
printf("\n============= SPI Bar ==============\n\n");
|
||||
|
||||
|
|
@ -461,23 +525,22 @@ static int print_spibar(struct pci_dev *sb, struct pci_access *pacc) {
|
|||
break;
|
||||
case PCI_DEVICE_ID_INTEL_EHL:
|
||||
/* the southbridge is the eSPI controller, we need to get the SPI flash controller */
|
||||
if (!(spidev = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 5))) {
|
||||
perror("Error: no spi device 0:31.5\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
rcba_phys = ((uint64_t)pci_read_long(spidev, 0x10) & 0xfffff000);
|
||||
rcba_size = 4096;
|
||||
if (!rcba_phys) {
|
||||
fprintf(stderr, "Error: no valid bar 0 of device 0:31.5 found %x %x\n", rcba_phys, rcba_size);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* this is not rcba, but we keep it to use common code */
|
||||
if (get_espibar_phys(sb, pacc, 5, 0x10, 0xfffff000, &rcba_phys))
|
||||
return 1;
|
||||
rcba_size = 4096;
|
||||
spibaroffset = 0;
|
||||
spi_register = elkhart_spi_bar_registers;
|
||||
size = ARRAY_SIZE(elkhart_spi_bar_registers);
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_HM470:
|
||||
if (get_espibar_phys(sb, pacc, 5, 0x10, 0xfffff000, &rcba_phys))
|
||||
return 1;
|
||||
rcba_size = 4096;
|
||||
spibaroffset = 0;
|
||||
spi_register = cometlake_spi_bar_registers;
|
||||
size = ARRAY_SIZE(cometlake_spi_bar_registers);
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_ICH:
|
||||
case PCI_DEVICE_ID_INTEL_ICH0:
|
||||
case PCI_DEVICE_ID_INTEL_ICH2:
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue