There were previously two functions manipulating the
SPI controller state: open_up_spi() and spi_init().
Combine the contents of open_up_spi() with spi_init().
Add the appropriate defintions in the SPI header.
BUG=chrome-os-partner:24624
BRANCH=baytrail
TEST=Built and booted. BCR and SCS register the same, as expected.
Change-Id: I108a3d3f55fa63e52960b6d42adca122547cab47
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/185140
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch overhauls the structure of the code that saves SDRAM
parameters to PMC registers for LP0 support, which had formerly been
very close to the U-Boot implementation. The new code keeps the
"translation table" entries as they are, but redefines the macros to
output hardcoded assignments instead of structure entries that need to
be parsed at runtime. It explicitly allows the compiler to merge and
reorder all accesses (under the assumption that PMC scratch registers
are essentially "like memory", without read or write side effects),
which generates much better and more importantly smaller code.
BUG=chrome-os-partner:25062
TEST=Nyan_big boots (on my Norrin, with the required board_id hacks) and
can suspend/resume fine to LP0. Measured (uncompressed) romstage size
for nyan_big at 25K without LP0 support, 43K with the old U-Boot style
implementation and 32K with this patch. Execution time of the function
drops from 1.2ms to .09ms.
Change-Id: Id52577c14d22ee67f167f10c3b976a037b1a321f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184388
This patch ports the code to save SDRAM parameters into PMC scratch
registers (for use by the BootROM on LP0 resume) from U-Boot. The
original "translation table" mechanism stays pretty much unchanged for
now, just simplified a few things and adapted it to our code flow. Gets
called unconditionally from the end of sdram_init() (which means we
won't support this for static BCT-style memory initialization).
BUG=chrome-os-partner:25062
TEST=Installed AVP LP0 handler blob that Dylan pulled out of U-Boot in
/lib/firmware/tegra12x/tegra_lp0_resume.fw. Confirmed that I can LP0
suspend/resume. Also compared PMC register dumps with a U-Boot system
and confirmed that there were no unexpected differences.
Change-Id: I9782967b43741c9ba19e24164a291dff7893ab1d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182928
To support arbitrary numbers of memory configuration, we are now ready to remove
SDRAM configurations from BCT and do SDRAM initialization in ROM stage.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan # Built successfully.
BRANCH=nyan
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: I06387075813f4f179323e264c4c0077445944291
Reviewed-on: https://chromium-review.googlesource.com/185114
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Tom Warren <twarren@nvidia.com>
This just moves FB_SIZE_MB to a more suitable location. It was likely
placed in addressmap.h originally since it was together with some
other constants which relied on config variables. But now those are
determined via helper functions instead.
BUG=none
BRANCH=none
TEST=compiled and booted on nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I9b03839bbe8924c313c45a81af85b3db6f464add
Reviewed-on: https://chromium-review.googlesource.com/184930
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
To support arbitrary numbers of memory configuration, we are now ready to remove
SDRAM configurations from BCT and do SDRAM initialization in ROM stage.
BUG=none
TEST=emerge-nyan_big chromeos-coreboot-nyan # Built successfully.
BRANCH=nyan_big
Change-Id: Id8673b9ec8c59e450d195758492d8e3484e02edc
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183624
The MemoryType field name should be CamelCase so we can convert directly from
BCT *.cfg files. The enum names for MemoryType are also changed.
BRANCH=none
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
Change-Id: I03d881edcf22a86710e6fb1ff60659b4f999868f
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/185113
With all the stuff we have been cramming into our romstage lately, 36KB
isn't really going to cut it anymore. While we should think about other
measures to keep our image size down for the sake of boot time, this
patch provides some quick relief to allow us to move on for a while. It
rearranges the iRAM layout to make more use of the pre-0x4000e000 region
after the BootROM is gone and reduces the size of the CBFS cache a bit
in favor of bootblock and romstage.
BUG=None
TEST=nyan_big boots on my Norrin, even if I have 16 SDRAM param tables.
Change-Id: I3072077978b1f34d222f1844491c5c038d433b85
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184240
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
This eliminates CONFIG_DRAM_SIZE_MB and uses helper functions to
determine DRAM size dynamically. It impacts MMU setup and BCT
selection in romstage, along with framebuffer setup in ramstage.
BUG=none
BRANCH=none
TEST=built and booted on Nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I41e6b24b853b856026fc26f3b1ee8edf2333ad3c
Reviewed-on: https://chromium-review.googlesource.com/184431
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
This adds a method for obtaining DRAM size from memory controller
registers. It is intended as an SoC-specific helper function that
can be used from very early ramstage code.
BUG=none
BRANCH=none
TEST=built and booted on Nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ib8b30e464b1398b78c5ffd8eada88b60d25ebf2b
Reviewed-on: https://chromium-review.googlesource.com/184535
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
These are cut from the hybrid 2/4GB BCT cfgs I
received, using just the 4GB section. Diffed against
the 2GB BCT cfgs already present and found logical
differences (mem size, etc). Untested as I have no
4GB system here.
These are named with the RAMCODE, speed and size
encoded in the filename. The CFG2INC script/tool
can use this info to place them at the proper
offset in the ramcode table as needed.
BUG=none
TEST=none, no code ready yet to receive these BCTs.
BRANCH=none
Change-Id: I5f8abc1e3b241064631cfa66c7f97c1804d9f9d4
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/184159
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Since Nyan Big board id pins may layout in tri-state, we need code
to support this change.
We use every two-bit to encode a gpio state as below:
b00: LOW
b01: HIGH
b10: TRI-STATE
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
coreboot log shows "Board TRISTATE ID: 0x41" for gpios 1001
Change-Id: I05d63f0bdafd533ef9d9e0da668837ecd2f4c8c0
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/183855
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Doug Anderson <dianders@chromium.org>
Similarly to lynxpoint payload loading can be made faster
by taking advantage of the spi controller's caching and prefetching.
Provide the same mechanism as lynxpoint to provide a 30ms
payload loading savings. The speed up isn't as dramatic as lynxpoint
presumably because baytrail is an SoC without the DMI communication
overhead. Regardless, payload loading decreases from ~55ms to ~25ms.
BUG=chrome-os-partner:25385
BRANCH=baytrail
TEST=Built and did numerous reboots. Observe time savings.
Change-Id: I5726d41559a8b4facb4bfdb7e629d04819dc9d37
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184853
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The linux kernel designware i2c driver supports configuring
HCNT/LCNT and SDA Hold Time for both standard and fast mode.
These have hardcoded defaults when the controller is in PCI
mode but it uses zero if nothign is defined in ACPI.
This adds the same default values that are in the kernel for
the controllers in PCI mode in magic packages that are read
by the kernel.
BUG=chrome-os-partner:24380
BRANCH=baytrail
TEST=build and boot on rambi
Change-Id: I249b0a217170c7189d633ad97d91361578a1838f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184922
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
GPIO_ACPI_SCI implies wake and generating an SCI. This
is unnecessary. Therefore, configure the intended wake
pins to only just wake by using GPIO_ACPI_WAKE.
BUG=none
BRANCH=baytrail
TEST=Manual. S3 resumes from keyboard and trackpad. No
excessive SCI's are generated.
Change-Id: I0b841e64909301e8d4789183ad53a016be7120f1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184719
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Previously the GPIO_ACPI_SCI meant generate an SCI
and wake the system. However, when using this configuration
for a device which has its interrupt line going to both
an interrupt pin and the wake pin SCIs are generated in
addition to the normal interrupt. This is unnecessary
and a waste of cpu cycles. Therefore provide the granularity
of waking but not generating an SCI. The GPIO_ACPI_SCI
still implies wake.
BUG=none
BRANCH=baytrail
TEST=Manually. Reconfigured pins with GPIO_ACPI_WAKE. Trackpad
and keyboard still wake the system without causing SCIs.
Change-Id: I437cc4501726835aadc4abf9bbaea3daebf68775
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184718
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This applies the same changes from 07a3592 that were applied to nyan.
BUG=none
BRANCH=none
TEST=it compiles.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Idcbe85436d7a2f65fcd751954012eb5f4bec0b6c
Reviewed-on: https://chromium-review.googlesource.com/184551
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
In order to play audio through a HDMI cable the
HDA device needs to be initialized and a the
verb table set up for the HDMI codec. Do this if
the HDA device is enabled.
BUG=chrome-os-partner:24908
BRANCH=baytrail
TEST=Built and booted with kernel changes to handle
baytrail hdmi codec. Benson confirmed sound
does come through hdmi.
Change-Id: I106fd20d8442a7ad7a47a144a1584eb311a0a583
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184710
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The kernel drivers have all been updated to use ACPI ID probing
methods and we can now put the I2C controllers in ACPI mode.
BUG=chrome-os-partner:24380
BRANCH=baytrail
TEST=build and boot on rambi, test that trackpad, als, sound still work
Change-Id: I50603eb48a557a5e82fd6510e42940a1f5379b87
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184530
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The C0 stepping wants the firmware ram information
in the MMIO space. However, the old method for informing
the driver of this location is maintained since there
is a dependency on the driver being updated.
Lastly, fix a bug for LPE in ACPI mode where the incorrect
base address value was being used for the firmware location.
BUG=chrome-os-partner:23791
BUG=chrome-os-partner:24380
BRANCH=baytrail
TEST=Built and booted on B3. Sound still works.
Change-Id: I747c133c20a330fd59ab2c8b64ac1bdcebaa9cd5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184481
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The toggling of XHCIBAR+80E0h[24] appears to cause the XHCI
controller to be reset on resume. This causes the kernel to
have to reinitialize the controller and all devices.
It seems this bit should only be toggled on boot path, in
the resume path it should be left as 0.
Additionally after routing ports to XHCI don't issue a port
reset to the ports in the resume path.
BUG=chrome-os-partner:25428
BRANCH=baytrail
TEST=build and boot on rambi, suspend/resume and look for usb errors
Change-Id: Ie2f02e4eda502fb670265627ed2968e0d47f3530
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184500
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The rest of the thermal configuration is in DPTF ACPI code so
move the CPU settings there as well.
Also remove the unused thermal.asl file.
BUG=chrome-os-partner:17279
BRANCH=baytrail
TEST=build and boot on rambi, start DPTF application
Change-Id: I9048e5d4504328603f34e5d0e14c110fdda01f67
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184443
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These can be used by DPTF with the CPU particpant and DTS
in addition to the external thermal sensors.
BUG=chrome-os-partner:17279
BRANCH=baytrail
TEST=build and boot on rambi, start DPTF application
Change-Id: I15df46183f4da4b2d7c8ee4687a71bff641d6b70
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184442
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This object is used by DPTF for power limiting in the CPU.
It is nominally set to the SdpProfile 2 values.
BUG=chrome-os-partner:17279
BRANCH=baytrail
TEST=build and boot on rambi, start DPTF application
Change-Id: I55f6a32cd61302dda6103745b22cb7233ad78b0b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184158
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch changes the ENTRY() macro in asm.h to create a new section
for every assembler function, thus providing dcache_clean/invalidate_all
and friends with the same --gc-sections goodness that our C functions
have. This requires a few minor changes of moving around data (to make
sure it ends up in the right section) and changing some libgcc functions
(which apparently need to have two names?), but nothing serious.
(You may note that some of our assembly functions have data, sometimes
even writable, within the same .text section. This has been this way
before and I'm not looking to change it for now, although it's not
totally clean. Since we don't enforce read-only sections through paging,
it doesn't really hurt.)
BUG=None
TEST=Nyan and Snow still boot. Confirm dcache_invalidate_all is not
output into any binary anymore since no one actually uses it.
Change-Id: I247b29d6173ba516c8dff59126c93b66f7dc4b8d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183891
This patch changes several cache-related pieces to be cleaner, faster or
more correct. The largest point is removing the old
arm_invalidate_caches() function and surrounding bootblock code to
initialize SCTLR and replace it with an all-assembly function that takes
care of cache and SCTLR initialization to bring the system to a known
state. It runs without stack and before coreboot makes any write
accesses to be as compatible as possible with whatever state the system
was left in by preceeding code. This also finally fixes the dreaded
icache bug that wasted hundreds of milliseconds during boot.
CQ-DEPEND=CL:183877
BUG=None
TEST=Snow and Nyan still boot. Time between entering romstage main() and
the configure_l2ctlr() call on Nyan drops from 390ms to 0.3ms. Even with
icache turned on the old implementation took 7.8ms since it cleared the
cache multiple times with a slow algorithm.
Change-Id: I7bb4995af8184f6383f8e3b1b870b0662bde8bd4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183890
This patch fixes the remaining few bugs in our shiny new cache iteration
by set/way/level algorithm to actually make it work: It makes it start
from cache level 0 (previously it would always start at LoC and be
"done" instantly), fixes up the two shifts that isolate the set bits at
the end (which didn't seem to account for the fact that the first shift
affects the second), and throws an S bit on that last shift so that it
actually affects the conditionals after it.
In addition, also moves the next_level block to the top so that we can
share (and thus eliminate) some code at initialization, and turns the
whole thing into a thrice-instantiated macro to create functions that
fit our existing interface.
BUG=None
TEST=Ran with cache_test code (see separate CL) and closely examined the
resulting output. Made sure results look as expected (iterating through
all sets (inner) and ways (outer) for L1 and then L2 cache, extracting
the right numbers from CLIDR and CCSIDR, not touching anything twice).
Time for a single dcache_clean_invalidate_all() on Nyan drops from 3.7ms
to 0.3ms.
Change-Id: I1338a589cbb37d74ea6e7a3d4f67ff827e24edbe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183879
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This patch pulls in NetBSD's full cache flushing algorithm for ARM, to
replace our old, slow and slightly overzealous C-only implementation.
It's a beautiful piece of code that manages to run on only caller-saved
registers (meaning it doesn't need to write to memory) in a very tight
loop, and it's BSD-licensed to boot (which we need for libpayload).
Unfortunately it's also not quite correct, but I can fix that. Pulling
the original in a separate commit to make it more obvious what changes
are mine.
BUG=None
TEST=None
Change-Id: I7a71c9e570866a6e25f756cb09ae2b6445048d83
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183878
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Cherry-picking https://chromium-review.googlesource.com/183833 for nyan_big.
BootROM uses RAM_CODE[3:2] value as index to retrieve boot device
array in BCT to reconfigure device. Since there will be one kind
of boot device, we can reuse RAM_CODE[3:2] in conjunction with
RAM_CODE[1:0] to select up to 16 RAM parameters. To support this
change without leading BootROM to read wrong boot device parameters,
we need to fill up boot device array.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan # boots successfully.
Change-Id: I0eb37ecf65ca041fe2f10c426b8dfbaafee24b2d
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184076
Reviewed-by: Julius Werner <jwerner@chromium.org>
The RAM_CODE on Tegra can be used to determine SDRAM configuration type.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan
Change-Id: Ica770ed6089f6ff8c38841f2cc8fd2778b6d786f
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183781
Reviewed-by: Julius Werner <jwerner@chromium.org>
To avoid throttling at low temps raise the passive threshold
to 60C until things are better calibrated.
Also add a dependency for the charger participant to the thermal
relationship table so when it is enabled it will be used properly.
BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi, start DPTF application
Change-Id: I4b50eff6a019b1cab0c781962a94c069ddbf0727
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184008
These GPIOs are defined in the mainboard and will be returned
as part of the LPE Device _CRS method.
BUG=chrome-os-partner:24380
BRANCH=rambi
TEST=build and boot on rambi
Change-Id: I7fe0852b63499530f6dfef4553e818e7364f4101
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184007
This adds an ACPI Device entry for the LPE Audio controller
and code to put the device in ACPI mode if set in devicetree.cb
The ACPI device attempts to append GPIOs that may be defined in
the mainboard-supplied ACPI code.
BUG=chrome-os-partner:24380
BRANCH=baytrail
TEST=manual: Build and boot on rambi with LPE in ACPI mode.
Without kernel support this is not very useful but it did show
that the device was no longer visible as a PCI device.
Change-Id: I44d5423f5bbea77e156012c071df6cb335fe658b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184006
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
792MHz BCT is from the board manuf, but boots fine on my
nyan. 924 BCT will be added later, when available.
BUG=none
TEST=builds and boots OK on my nyan board with depthcharge
changes for board id 0 in nyan_big.
BRANCH=none
Change-Id: I35f04dd7520ed9471287b2ecdbc1f0508bd78b6c
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/183975
Reviewed-by: David Hendricks <dhendrix@chromium.org>
PMIC VDD_CPU voltage is always 1.2V, so skip board_id check.
204MHz BCT is from the board manuf, but boots fine on my
nyan. 792/924 BCTs will be added later, when available.
BUG=none
TEST=builds and boots OK on my nyan board with depthcharge
changes for board id 0 in nyan_big.
BRANCH=none
Change-Id: Ib26bed66414b4a0943f3cfd5de907d7135a69152
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/183939
Reviewed-by: David Hendricks <dhendrix@chromium.org>
To support memory initialization without BootROM (which allows better
customization, updatable DRAM init procedure, and supporting more SDRAM
configurations that BootROM cannot handle), a new function "sdram_init(param)"
is introduced.
The input must be a "struct sdram_params", which has exactly the same layout as
the SDRAM fields in standard BCT file.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan # Boots successfully
Change-Id: I36a26fb5236eee8f329e3f84cbdcc1ec6992fe6b
Reviewed-on: https://chromium-review.googlesource.com/182615
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
The new clock_sdram(...) initialized PLLM by given configuration (which needs to
be explicitly determined, usually from BCT or SDRAM parameters).
BUG=none
TEST=emerge-nyan chromeos-coreoot-nyan
# With other patches, the new function starts PLLM in correct clock.
Change-Id: I606d0506c734d312db9e1b72a910700ca766f2d3
Reviewed-on: https://chromium-review.googlesource.com/183621
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
This is a cpu supported by the foundation emulator. This will not build
at all without my cbfstool changes.
Not that our chromiumos qemu for x86 is months behind upstream.
BUG=None
TEST=breaks no builds
BRANCH=None
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Change-Id: I0e7df1a2d3801778e83c89ff18285b026403adc0
Reviewed-on: https://chromium-review.googlesource.com/180355
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Ronald Minnich <rminnich@chromium.org>
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@chromium.org>
BootROM uses RAM_CODE[3:2] value as index to retrieve boot device
array in BCT to reconfigure device. Since there will be one kind
of boot device, we can reuse RAM_CODE[3:2] in conjunction with
RAM_CODE[1:0] to select up to 16 RAM parameters. To support this
change without leading BootROM to read wrong boot device parameters,
we need to fill up boot device array.
BUG=none
TEST=emerge-nyan chromeos-coreboot-nyan # boots successfully.
Change-Id: I901e052bc785561cfcb25fb24cf4629572af390a
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/183833
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
The name snow goes by in many places in chromeos is daisy. Snow is technically
a variant of daisy and should really be called daisy_snow, but for historical
reasons the daisy board with no variant was used instead. To make it easier to
work with within chromeos, this change renames the snow board to daisy.
BUG=None
TEST=Built for daisy.
BRANCH=None
Change-Id: I569b31bf417db55be91832f15271bea4bc30f163
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/183553
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The name pit goes by in many places in chromeos is peach_pit, where peach is
the base name and pit is the name of this particular variant. To make it
easier to work with within chromeos and to make the board names a little less
ambiguous, this change renames the pit board to peach_pit, and from Pit to
Peach Pit.
BUG=None
TEST=Built for peach_pit.
BRANCH=None
Change-Id: I51c89ba3785cf4cb9769a989b1cac71bcd1b0a05
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/183552
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
The nyan_big mainboard is very similar to nyan, but will be different in a few
ways. For instance, the BCT will be different, and the GPIOs may need to be
configured slightly differently.
This change also adds prefixes to the kconfig variables in "choice" blocks
for both boards since having multiple instances of choice blocks with the same
options confuses kconfig even if all of the instances have mutually exclusive
dependencies.
BUG=None
TEST=Built for nyan and nyan_big.
BRANCH=None
Change-Id: I290a32e47fc118bd4b86d543df617ad324325dbc
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/183532
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Some slow monitors/TVs can't wake up quickly enough for coreboot,
so when the VBIOS is run it won't detect them. Hence, add an option
to wait for a while before running the VBIOS.
BUG=none
BRANCH=panther
TEST=Boot to dev mode on one of the systems that exposed the problem
and see it go away.
Change-Id: Ib9524f1c7ee08bedf96a6468da8b4ccf712fe0e2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/183545
Reviewed-by: Mohammed Habibulla <moch@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The GPIOs were not being put into SCI mode to enable
their respective interrupt lines as wake sources. Also
the bit index into the GPE block was incorrect. Fix
both of these issues.
BUG=chrome-os-partner:25251
BRANCH=baytrail
TEST=Noted the appropriate bit was enabled for wake.
Also was able to wake with the track pad.
Change-Id: Ia1b6e4c8cb4b012d76ad27a2158e28d183581025
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183598
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The _PRW method needs to specifcy a bit number within
the GPE block to enable wake events associated with a
given device. Therefore, add ACPI_ENABLE_WAKE_SUS_GPIO()
macro for the mainboards' convenience.
BUG=chrome-os-partner:25251
BRANCH=baytrail
TEST=On rambi used macros for touch pad and screen. Noted
the appropriate bit was enabled for wake. Also was
able to wake with the track pad.
Change-Id: I98d7c005997bdcaa3646fabec5199fbe013ca52c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183597
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
In order to boot from G3 quickly disable the
slp_x stretching policy.
BUG=chrome-os-partner:25269
BRANCH=baytrail
TEST=Manual. Put board in G3. Pressed power button
and noted startup time on the EC console.
Change-Id: I039de7990cc6ff519d873d64756c8d119b131165
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183588
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Provide an option for the mainboard to set in its devicetree
to disable slp_x stretching on SUS power well failure. This
will allow for fast G3->S0 transition instead of waiting for
1-4 seconds.
BUG=chrome-os-partner:25269
BRANCH=baytrail
TEST=Manual. Enabled option. Put board in G3. Pressed power button
and noted startup time on the EC console.
Change-Id: I213525b3ad44fe4c95bfd014b614bbc80623cbb8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183587
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
