Duncan Laurie 0457b5dce1 baytrail: Fix XHCI controller reset on resume ... The toggling of XHCIBAR+80E0h[24] appears to cause the XHCI controller to be reset on resume. This causes the kernel to have to reinitialize the controller and all devices. It seems this bit should only be toggled on boot path, in the resume path it should be left as 0. Additionally after routing ports to XHCI don't issue a port reset to the ports in the resume path. BUG=chrome-os-partner:25428 BRANCH=baytrail TEST=build and boot on rambi, suspend/resume and look for usb errors Change-Id: Ie2f02e4eda502fb670265627ed2968e0d47f3530 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/184500 Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2014-01-31 18:31:28 +00:00
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arch	arm: Put assembly functions into separate sections	2014-01-29 21:33:41 +00:00
console	ARM: Generalize armv7 as arm.	2013-10-02 09:18:44 +00:00
cpu	cpu/intel: allow non-packaged scoped turbo setting	2014-01-15 04:52:13 +00:00
device	pnp: Allow setting of misc register 0xf4 in device tree	2013-12-20 00:37:38 +00:00
drivers	Haswell/falco/peppy/slippy: continue to clean up FUI.	2013-12-19 01:17:37 +00:00
ec	chromeec: add function to reboot on unexpected image	2014-01-10 00:11:54 +00:00
include	baytrail: snapshot power state in romstage	2014-01-09 20:15:55 +00:00
lib	baytrail: snapshot power state in romstage	2014-01-09 20:15:55 +00:00
mainboard	rambi: Move the CPU passive/critical threshold config to DPTF	2014-01-30 21:39:50 +00:00
northbridge	haswell: Allow pre-graphics delay	2014-01-25 02:03:21 +00:00
soc	baytrail: Fix XHCI controller reset on resume	2014-01-31 18:31:28 +00:00
southbridge	libpayload: find source of input characters	2014-01-19 04:15:03 +00:00
superio	pnp: Allow setting of misc register 0xf4 in device tree	2013-12-20 00:37:38 +00:00
vendorcode	VBOOT: Set virtual recovery switch based on EC Software Sync	2014-01-23 19:32:35 +00:00
Kconfig	armv8: add support for armv8 cpu	2014-01-07 02:48:47 +00:00