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nyan_big: apply cache-related changes from nyan

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This applies the same changes from 07a3592 that were applied to nyan.

BUG=none
BRANCH=none
TEST=it compiles.
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Idcbe85436d7a2f65fcd751954012eb5f4bec0b6c
Reviewed-on: https://chromium-review.googlesource.com/184551
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
David Hendricks 2014-01-31 16:31:49 -08:00 • committed by chrome-internal-fetch
commit 4af27f0261
1 changed files with 8 additions and 15 deletions
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23
src/mainboard/google/nyan_big/romstage.c
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@ -72,25 +72,12 @@ static void configure_l2actlr(void)
write_l2actlr(val);
}
void main(void)
static void __attribute__((noinline)) romstage(void)
{
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t romstage_start_time = timestamp_get();
#endif
// Globally disable MMU, caches and branch prediction (these should
// already be disabled by default on reset).
uint32_t sctlr = read_sctlr();
sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I);
write_sctlr(sctlr);
arm_invalidate_caches();
// Renable icache and branch prediction.
sctlr = read_sctlr();
sctlr |= SCTLR_Z | SCTLR_I;
write_sctlr(sctlr);
configure_l2ctlr();
configure_l2actlr();
@ -104,7 +91,6 @@ void main(void)
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
mmu_disable_range(0, 1);
dcache_invalidate_all();
dcache_mmu_enable();
/* For quality of the user experience, it's important to get
@ -140,3 +126,10 @@ void main(void)
#endif
stage_exit(entry);
}
/* Stub to force arm_init_caches to the top, before any stack/memory accesses */
void main(void)
{
asm ("bl arm_init_caches" ::: "r0","r1","r2","r3","r4","r5","ip");
romstage();
}