- Rephrase some items
- Add additional code examples
- Add additional sections
- Update documentation to the current state of the codebase.
Change-Id: I6e4cc244edf6cc860cc66165173f134a30a81589
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Linux (bzImage) payloads used to be totally not compressed with
cbfstool. However, only bzImage is already compressed and initrd is
usually compressed, but the trampoline, parameter, and kernel command
line should be compressible.
Now cbfstool can copy segments instead when compression fails, so
compression for Linux payloads (including LinuxBoot) could be enabled
for compressible components.
TEST=With LZMA, parameter is compressed from 0x1000 to 0x4c,
trampoline is compressed from 0x171 to 0x14b, kernel command line
is not compressed for being too short (0x22), initrd is not
compressed for being already compressed.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I8af3c904de55910a1298673d8ec2925a317bcff5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
When compression fails (usually due to larger result), we could retry
with memcpy() as in cbfs-mkpayload.c, instead of stopping immediately.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Id8b2cffef3832c4bad49bd722c9a5133735f61b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87934
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The IOT version of FSP is inconsistent at resuming from S3,
so switch to the client version.
Change-Id: Ifadfebf53e20bc82e6272ea28e5bc443b9829545
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88055
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Replace the existing TWL FSP headers, which were copied from ADL-N,
with the actual TWL headers.
TEST=starlabs byte_twl passes abuild w/o using IOT FSP.
Change-Id: I5c2836e81dee47dee73b14ce02f7bb8d0e846135
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This algorithm minimises the per-channel, per-lane digital COMP offsets
by adjusting the global COMP offset accordingly. The purpose of this is
not fully known, but it is likely to prevent saturation of per-channel,
per-lane registers during subsequent training steps, which NRI does not
implement yet. Some of the COMP offset functions are generic since they
are also used in said training steps.
Tested on Asrock B85M Pro4, still boots to Arch Linux.
Change-Id: Idb03c6c5ed85a522ff1b55905f522211d1472bd9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87833
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Builds using SBOM were failing in the release because we don't have a
git tree to get information from. We can't assume that the coreboot
source will always be in a git tree, so it needs to be updated. This
updates build.h to contain all the data that the SBOM wants and changes
the SBOM makefile to get its information from build.h which can generate
the required data in a number of different ways.
Change-Id: I59fba349d95cb0dcff7a31d335f4acb4f11c89c7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88236
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This commit updates the platform reporting logic to recognize the
Wildcat Lake SoC CPU ID.
Key changes:
- Add CPUID_WILDCATLAKE_A0 to the list of recognized CPU IDs in
the platform reporting module.
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I8c9e81446a12ee0a6e18f1ba3f36166652a05f5e
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88271
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit introduces a new MCH device ID to support the Wildcat
Lake SoC. It updates the PCI device ID list and platform reporting
logic to accommodate this new ID.
Key changes:
- Add PCI_DID_INTEL_WCL_ID_3 (0xfd02) to the list of recognized
device IDs.
- Update system agent operations to include the new MCH ID.
- Enhance platform reporting to recognize the new MCH ID.
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I464fb147f0d3df214ca64b1321eebab08505d7bc
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88248
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Enable Realtek ALC722 and ALC1320 soundwire codec for francka.
Refer to the main board schematic(1224A) and
audio board schematic(1106A).
BUG=b:420516709
TEST=Build and boot and check the ssdt dump PCI0.HDAS.SNDW.
Scope (\_SB.PCI0.HDAS.SNDW)
Device (SW00)
Name (_ADR, 0x000030025D072201) // _ADR: Address
Name (_DDN, "Headset Codec") // _DDN: DOS Device Name
Scope (\_SB.PCI0.HDAS.SNDW)
Device (SW20)
Name (_ADR, 0x000230025D132001) // _ADR: Address
Name (_DDN, "Speaker Amp") // _DDN: DOS Device Name
Scope (\_SB.PCI0.HDAS.SNDW)
Device (SW30)
Name (_ADR, 0x000330025D132001) // _ADR: Address
Name (_DDN, "Speaker Amp") // _DDN: DOS Device Name
Change-Id: I542d94fd792272d3b7d75538671ba2f59c331a1e
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88022
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Because of the internal misunderstanding, so now correct the right fw
config of wifi SAR id number from 18 to 21 to 17 to 20.
BUG=b:395763555
BRANCH=none
TEST=Build and boot to OS and check coreboot log to check the wifi SAR table could work fine.
Change-Id: Ib006996fb8887a36feb5dfe71baef58fa74c35f7
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88200
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due to a recent acpica version upgrade, the acpica tool is now
failing to download due to an incorrect url. This commit aims to
fix the issue by updating the iasl base url to match the upgraded
version.
Change-Id: I7eddff2d17587f5d90295928800c10068c8cf281
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The power LED may be disabled by GPP_D1. The pin is PWM capable, so
configure it in PWM mode with a frequency of 0.5Hz, duty cycle of 50%
when entering sleep.
The result is that the power LED toggles on/off every second.
TEST=Boot to Windows 10, enter S3, and wake. The power LED will blink
when system is asleep and glow continuously when awake.
Change-Id: I121e0ef3e47aec1cacdace3f2af47a3fdacf69cf
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Correct UART1 TX/RX pad configuration in early_gpio.c from NF2
to NF1. This enables proper UART1 signaling on GPP_D17 and GPP_D18
when operating in native mode.
This change is based on guidance from Intel Doc. No. 648094.
TEST=Patched and booted board. Confirmed UART1 communication
works via serial adapter. Loopback test passed.
Change-Id: Ib1f5ee17e6f3d8a845d024e6b8593606b0430b6f
Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88195
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updated DDI port configuration to properly enable eDP (Port A)
and HDMI (Port B) with HPD and DDC settings on LattePanda MU.
This change ensures both internal and external displays are
detected and initialized correctly during boot.
Change-Id: I84e5bc4b8a26f58b9cb26a4018eef640ac245e7f
Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88194
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable Intel PMC and ACPI IPC interface in Kconfig to fix
power-off failure on shutdown.
Previously, the system failed to fully power off after shutdown,
leaving some power rails active and preventing restart via the
power button. A full power cycle was required to reboot.
This change ensures proper system power-off behavior.
TEST=Tested shutdown behavior with PMC and ACPI IPC interface
enabled in Kconfig. System now powers off cleanly and can restart
via power button without unplugging power
Verify OS: Ubuntu 24.04
Change-Id: I1f93410bcd717630319adabec40534b5b7467582
Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88193
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add `board.fmd` and update Kconfig to define FMDFILE for
LattePanda MU.
This file describes the flash layout including
- Flash Descriptor
- ME
- MRC_CACHE
- SMMSTORE
- CBFS
TEST=Built mb/lattepanda/mu with and without board.fmd.
Adjusting FMAP layout via board.fmd changes section sizes and offsets.
This affects the position and size of the COREBOOT (CBFS) region in
the final ROM image.
With board.fmd:
- FMAP layout explicitly defines COREBOOT size and offset
- build log shows detailed FMAP section breakdown, including
CBFS region
Sample log excerpt:
'COREBOOT' (CBFS, size 3865600, offset 12911616)
Without board.fmd:
- default FMAP layout is applied
- COREBOOT region is located differently
with board.fmd
```
Writing new image to build/coreboot.pre
UPDATE-FIT set FIT pointer to table
UPDATE-FIT Microcode
CBFS coreboot.rom
FIT table:
Index Type Addr Size
0 Microcode 0xffc504b0 0x00000000
CBFSLAYOUT coreboot.rom
This image contains the following sections that can be manipulated
with this tool:
'SI_DESC' (size 4096, offset 0)
'SI_ME' (size 4272128, offset 4096)
'SI_PDR' (size 2015232, offset 4276224)
'RW_MRC_CACHE' (size 65536, offset 12582912)
'SMMSTORE' (size 262144, offset 12648448)
'COREBOOT' (CBFS, size 3865600, offset 12911616)
...
Built lattepanda/mu (MU_8G)
```
without 'board.fmd'
```
Writing new image to build/coreboot.pre
UPDATE-FIT set FIT pointer to table
UPDATE-FIT Microcode
CBFS coreboot.rom
FIT table:
Index Type Addr Size
0 Microcode 0xffc502b0 0x00000000
CBFSLAYOUT coreboot.rom
This image contains the following sections that can be manipulated
with this tool:
'SI_DESC' (size 4096, offset 0)
'SI_ME' (size 4272128, offset 4096)
'SI_DEVICEEXT2' (size 2015232, offset 4276224)
'RW_MRC_CACHE' (size 65536, offset 12582912)
'SMMSTORE' (size 262144, offset 12648448)
'COREBOOT' (CBFS, size 3866112, offset 12911104)
...
Built lattepanda/mu (MU_8G)
```
Change-Id: If197679c8359f5f75ab125b0c8600926611ac57b
Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88192
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add parameters and default setting of FSP
BUG=b:407645233
TEST= IOMT verification confirmed, that USB settings can be updated through FSP parameters.
Change-Id: Idbd9ee795b74f43921472ef42a95b2be23af6f5d
Signed-off-by: Doris Hsu <doris.hsu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add eDP panel power-on sequences and initialize the display in the
ramstage. Also Set display registers to normal mode if initialization
flow is skipped to prevent abnormal behavior.
BUG=b:400886838,b:422507985
BRANCH=none
TEST=utility gbb --set --flash --flags=0x39, and check the firmware
screen.
utility gbb --set --flash --flags=0x0, and check the DUT screen.
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.corp-partner.google.com>
Change-Id: I09edceefee9c17ce18681b85da8ca75f65ed2876
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88273
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Extract code for disabling secure mode from mtk_ddp_init and implement
it as mtk_display_disable_secure_mode(). This allows disabling display
secure mode without using DDP, for example, when FW display is not
needed.
Unlike previous SoCs, MT8189 is designed so that access to display
registers defaults to secure mode, due to specific product requirements.
However, Chromebook products do not use this setting and instead require
the register permissions to be set for normal mode access, consistent
with previous SoC behavior.
Also reordered function declarations to group similar types (e.g.,
display, DDP) together for better readability.
BUG=b:422507985
BRANCH=none
TEST=utility gbb --set --flash --flags=0x0, and check the DUT screen.
Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ic378ef62540c408ccd59e482abfe9f9c8ca5a13d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Add support to enable QUPV3, QSPI and GPLL0 clocks. Modify
XO Source clock frequency value to 19.2KHz. The register
details are part of HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/
TEST=Create an image.serial.bin and ensure it boots on X1P42100
Change-Id: I6252bc1fda3c53a683c65d2ab4a3b9f27ea64618
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The register layout for QUP has been updated in QUP v3.2. Update the
structure definition accordingly. Allow SoCs to use the existing version
or the updated version based on QC_COMMON_QUPV3_2.
Change-Id: I304012d72a1af33510dcd620953367f0a9e98ac1
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88190
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the EC host command range configuration for Ocelot
board variants, ensuring that each variant uses the correct range based
on its specific EC.
BOARD_GOOGLE_OCELOTMCHP and BOARD_GOOGLE_OCELOTMCHP4ES uses Microchip
EC.
BOARD_GOOGLE_OCELOT and BOARD_GOOGLE_OCELOT4ES uses Nuvoton EC.
BOARD_GOOGLE_OCELOTITE and BOARD_GOOGLE_OCELOTITE4ES uses ITE EC.
Key changes:
- Microchip EC: Configured to use host command ranges 0x800-0x807 and
0x200-0x20f. The register is set to 0x00040801 to accommodate these
constraints.
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: If08f2362a7b3bafca69375ce3b346f75435a83df
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88179
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A compaq_8300_elite_sff build can run on these models mostly unmodified.
Spawn a new variant from it, tie up some obvious loose ends and bring it
officially into the fold.
BUG=https://ticket.coreboot.org/issues/581
Change-Id: Ic0f04d586a8361968d7f6c3e3d048f945528cb84
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
In order to support runtime evaluation of the TPM base address
introduce and use a new method for CRB TPMs.
Change-Id: I29c81d82947eb2603472a515f9ada598e4f8e6ea
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Add support for the Memsic MXC6655 accelerometer on I2C0, as an
alternative to the existing Kionix KCXJ9. Use the "detect" function
of the I2C generic driver to determine which is present at runtime.
TEST=build/boot starlite_adl with MXC6655, verify screen roation works
properly when detached from keyboard under Linux and Windows.
Change-Id: I59d424903cceda9871855372e1d666eaa12443b0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Load PI image through CBFS and pass parameters of PI image to mtk_fsp
for parsing.
BUG=b:379008996
BRANCH=none
TEST=check the boot log:
[INFO ] CBFS: Found 'pi_img.img' @0x3d880 size 0x10b in mcache @0xfffdd314
[DEBUG] mtk_init_mcu: Loaded (and reset) pi_img.img in 14 msecs (720 bytes)
Signed-off-by: Hope Wang <hope.wang@mediatek.corp-partner.google.com>
Change-Id: Iada90ad4298d0a91ad73798252db19b12f2f6ef7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88266
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
To promote code reuse and maintainability, move PI image related code to
common folder. The function add_pi_image_params is renamed to
pi_image_add_mtk_fsp_params for prefix consistency.
BUG=b:379008996
BRANCH=none
TEST=build passed.
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: If5e3d9e6d5f97ead763ef9adc2d23bce0ed68877
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88265
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The QCOM X1P42100 SoC requires images loaded by PBL in MBN v7
format. This script is updated to support MBN v7 format which will
be used to generate the Bootblock binary.
Starting with the Qualcomm x1p42100 SoC, the bootblock ELF header
expects MBN version 7 instead of version 6 with the SC7280 SoC. This
patch adds the necessary adjustment to ensure compatibility with older
SoC platforms and also adds incremental support for newer SoC
generations. If Qualcomm SoCs in the future demands a more advanced
version of MBN (version > 7), additional logic will be added to the
newly added section as `self.flash_parti_ver == 8`.
BUG=b:420542130, b:404985109
TEST=Create image.serial.bin with bootblock in MBN v7 format and
ensure it boots on X1P42100. Please refer to the steps mentioned
below to create final AP FW image for QC SoC X1P42100.
Step 1: Create Bootblock MBN image using createxbl.py script where the
newly added MBN v7 support will be used.
Step 2: Call create_multielf.py to create the concatenated multi ELF
( TME SEQ + TME FW + QC_SEC + BOOTBLOCK from step 1)
Step 3: Call nqgpt.py to create final GPT image.
Change-Id: I484df537ac7d1e51ec86dcae74a74dc211710616
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88240
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit refines the ROM size configuration for Google Bluey
mainboards by moving the `BOARD_ROMSIZE_KB_*` selection from the
common Kconfig to the specific board variants.
Previously, `BOARD_ROMSIZE_KB_65536` was selected for
`BOARD_GOOGLE_BLUEY_COMMON`. This blanket setting is inaccurate as
different Bluey-based boards utilize different sized ROMs.
With this change:
- `BOARD_GOOGLE_BLUEY` now selects `BOARD_ROMSIZE_KB_65536`.
- `BOARD_GOOGLE_QUENBI` now selects `BOARD_ROMSIZE_KB_32768`.
This ensures that each board variant has the correct ROM size
configured, preventing potential issues related to image size or
flash programming.
TEST=Able to verify that google/bluey AP FW image os 64MB and
google/quenbi AP FW is 32MB in size.
Change-Id: Ifcf75b310f08cbc4bbbd27ad7947df06da4f5d5a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit refactors the SPI flash vendor selection for Google Bluey
boards to accurately reflect the components used by each variant.
Previously, `SPI_FLASH_WINBOND` was unconditionally selected for
`BOARD_GOOGLE_BLUEY_COMMON`. This is incorrect as different Bluey
variants may use different SPI flash chips.
This change now specifically selects:
- `SPI_FLASH_MACRONIX` for `BOARD_GOOGLE_BLUEY`
- `SPI_FLASH_WINBOND` for `BOARD_GOOGLE_QUENBI`
This ensures that the correct SPI flash driver is enabled for each
specific board variant, as per underlying hardware design.
TEST=Able to build google/bluey.
Change-Id: I7deaed90a7f6533ed4fe9fd815715dabdaa561a3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit enables `ARM64_USE_ARM_TRUSTED_FIRMWARE` for the
Qualcomm X1P42100 SoC.
Selecting this option ensures that coreboot is configured to
integrate with ARM Trusted Firmware (TF-A), which is essential
for proper boot and power management functionality on this platform.
BUG=b:424149462
TEST=Able to build google/bluey.
Change-Id: I30bc3eb9eedcaaef67cccf8c2f29c6ed76c71e9a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
permanent_smi_handler and acpi_s3_resume_allowed returns boolean,
so use boolean instead of int.
Change-Id: I8f390bf3b472519dc41db7daa57b16458961139e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
enable_power_saving is a boolean so use "true" "false".
Change-Id: I0f62fc2b0db3abd3f204951f15081b89e02a0754
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86608
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8189 is equipped with the Power Mode Resource Collector (PMRC)
feature, and the implementation to set PMIF to normal mode is the same
as in pmif_spmi_v2. Use pmif_spmi_v2 to correct the configuration to
allow PMIF to properly enter normal mode on MT8189.
BUG=b:379008996
BRANCH=none
TEST=check the following logs for PMIC communication
[DEBUG] pmic_efuse_setting: Set efuses in 10 msecs
[INFO ] [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
[INFO ] [RTC]rtc_boot,330: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
[INFO ] [RTC]rtc_enable_dcxo,66: con=0x486, osc32con=0xfe69, sec=0x0
[INFO ] [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
[INFO ] [RTC]rtc_osc_init,62: osc32con val = 0xfe69
[INFO ] [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: Ib3eeba7ca9bd446b641a17fbe97bcda373cb4a24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88244
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
brox_rtk_ec share the same power design with brox,
so follow brox set as 9W.
BUG=b:414474440
TEST=system can boot when AC only.
Change-Id: Ia05b331f229127b898f4549d5ba1ac2771ac8b7b
Signed-off-by: Elmo Lan <elmo_lan@realtek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
compiler-rt is not a variable used by the LLVM_ENABLE_PROJECTS config,
but has a separate configuration option.
Change-Id: Iacd9b5f1fc1444b3dd1a785b91510f346e7a2f51
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80737
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
