Handle ADL-P and ADL-M PCI IDs the same as ADL-N and RPL-P for
dumping LPC registers. Add southbridge names/labels for ADL-P
and ADL-M.
TEST=build and run 'inteltool -l' to dump LPC/eSPI registers on
google/taeko (RPL-P), verify output matches LPC decode set in devicetree
Change-Id: I84901a8e25eb679acb31be1caa8fffa667454c62
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91026
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In a follow-up patch (CB:90962), the list will be changed to a circular
one, and list_node fields 'next' and 'prev' will become private to the
implementation.
To allow smooth transition to circular lists for all call sites, add the
following functions to the list API:
- list_is_empty()
- list_next()
- list_prev()
- list_first()
- list_last()
- list_length()
All list API call sites are expected to use the public API instead of
the raw 'next' and 'prev' pointers.
Change-Id: Ib1040f5caab8550ea52db9b55a074d7d79c591e5
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The code was copied from newer generation SoC supporting parallel
SMM relocation, but it wasn't properly cleaned.
Gen1 doesn't support parallel SMM relocation, so fix the comments.
Change-Id: Idbe6d2c18f668a9c1922b93ce1b2cc3d126ff2f9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91013
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As discussed under CB:88768, building for PantherLake targets fails due
to odd race-condition:
```
src/include/stdint.h:66:9: error: "INT32_MAX" redefined [-Werror]
66 | #define INT32_MAX ((int32_t)0x7FFFFFFF)
| ^~~~~~~~~
[...]
129 | #define INT32_MAX (0x7FFFFFFF)
| ^~~~~~~~~
cc1: all warnings being treated as errors
make: *** Waiting for unfinished jobs....
```
Board maintainers shouldn't need to include the FSP API header in their
ports, adding this header globally to meminit.h resolves the
race-condition and allows the build to finish.
Change-Id: Id7656d476ca6db78ea74629ef37a20323362997a
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91023
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Commit dd817408e1 ("device/pci_device: Fix leftover devices") changed
the conditions for a device to be considered leftover to include not
being disabled, so update the comment to reflect that.
Change-Id: If80a5aae00ba97c1e0580dedb460a605a71bb627
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Make PCIe ASPM/L1SS CFR options depend on PCIe Clock Power Management
so the setup UI can hide them when CLK PM is disabled.
Change-Id: I7dc778bc2d6fb15d6062a4ab855bc8b700c22fad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The touchscreen device is dependent on the accelerometer on starlite_adl,
so offer the touchscreen CFR option only when the accelerometer option is
enabled.
Implement a new weak cfr_touchscreen_update() callback in the starlabs
common CFR code and override it in starlite_adl to suppress the
touchscreen option when accelerometer is disabled
Change-Id: I4bab6ccb92c40190014ab55200ff214064d5d2ae
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Update platform_romstage_pre_mem() to only trigger the red LED alert
when the lid is closed.
Previously, the critical low battery alert would trigger regardless of
the lid state. Checking the lid switch ensures the visual alert is
targeted at "closed-lid" scenarios where the user needs a physical
indicator of a power-critical state that prevents booting.
Change-Id: I9833fb26df9c31989abec142536e1fe7efb93c10
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested on a HP ProDesk 400 G7, with an i5-10500 and a Q470 chipset.
Dumping MCH, SPI/BIOS CONTROL, LPC/eSPI, GPIO, EPBAR and DMIBAR work.
Change-Id: I0eca3a72c42b0cb85bcda8502bccbb4a80704b3b
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The GPIO pad community definition for Skylake does not set the
pad_cfg_lock_offset member, leading to an "offset not defined for pad"
error when trying to lock a pad config in gpio_non_smm_lock_pad(). This
must be set to the offset of the first Pad Configuration Lock register
within each GPIO communities register blocks which can be found in the
GPIO sections of the processor I/O and PCH-H datasheets.
References:
Skylake-U/Y: Intel 332691
Sunrise Point-H: Intel 332996
Kaby Lake-U/Y: Intel 334659
Union Point-H: Intel 335193
Change-Id: I2991a7cbfb333d9fdda008cbb4cbc272aa508ef0
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
According to EDS #872188, PTL-H484 has 8 more PCIe
lanes than PTL-H404 and 12Xe SKUs.
I believe there's been a mixup during bringup, as PCIe ACPI tables are
"gated" for an SKU with more PCIe 5.0 lanes.
To be exact, in a file: "src/soc/intel/pantherlake/acpi/ptl_pcie.asl"
we can notice PCIe 5.0 RootPorts depending on SOC_INTEL_PANTHERLAKE_H.
Google/Fatcat boards seem to be using PANTHERLAKE_U_H instead.
TEST: Build/boot intel/pantherlake_crb. Make sure Linux doesn't report
PCIe routing errors.
Change-Id: I1d136cf1959a3851d0ac37b256fd4df28a8d30df
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Generate an 'EMMC' ACPI device under the PCIe root port to which the
GL9763E is attached. The EMMC device contains a child CARD device whose
_RMV method returns 0. This allows Windows to identify the eMMC as a
fixed internal drive instead of a removable one.
This fixes an issue where the Windows 11 installer fails around 55%
with a generic 'Windows 11 installation has failed' error. Install
logs show the failure is due to Windows identifying the storage
device as removable and aborting (error 0xC1420134).
TEST=build/boot Win11 installer on google/taeko with eMMC installed,
verify Windows installer identifies it as a non-removable drive via
diskpart, and install completes successfully.
Change-Id: I51e59cb9e9dc2459724138b4bd404fb1eea64680
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Revised the GPP_E18 configuration to use GPI IRQ.
BUG=b:473955137
TEST=Confirmed that the ELAN touchpad functionality
is operating correctly,and no occurrences of the
following error message are observed in the logs:
elan_i2c i2c-ELAN0000:00: invalid report id data (0)
Change-Id: Ie8fd2f13f5db4f830e4ffcd88a5a7b55f4d9bee3
Signed-off-by: Pierce Chou <chou.pierce@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90908
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current clang version cannot be built using GCC-15 so switch to a
more recent release.
It also adds a new dependency called third party. Its used in various
LLVM components and is needed to build clang.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I0f2ebc214726fd4ae4f7bba50a662dd5cb89a718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89377
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set PcieRpSlotImplemented to 0 on the PCIe root ports which have eMMC
attached via a GL9763E bridge/controller for chronicler and elemi
variants. This ensures that FSP correctly treats these RPs as built-in
rather than slot devices.
TEST=tested with rest of patch train
Change-Id: I0e06df689164f95ee9f0253fde3df2891239fa63
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Set the PCIE_RP_BUILT_IN flag on the PCIe root ports which have eMMC
attached via a GL9763E bridge/controller for all variants using PCIe-
attached eMMC. This ensures the FSP PcieRpSlotImplemented UPD is set
properly and that FSP correctly treats these RPs as built-in rather
than slot devices.
TEST=tested with rest of patch train
Change-Id: Ifb4b255ea5367733405a7ac5d73c616ce7f8aad5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
The existing Lynx Point code is known to work with 9 series PCHs, as
evidenced by commit f5105313cf ("mb/asrock/z97_extreme6: Add new
mainboard") and commit 58c7a84097 ("mb/asrock: Add Z97E-ITX/ac
(Haswell/Broadwell)"). Add the missing IDs to autoport's existing Lynx
Point code.
These IDs were taken from the Intel 9 Series Chipset Family Platform
Controller Hub datasheet (document 330550), section 1.4 "Device and
Revision ID Table".
TEST=Autoport output for the ASRock Z87E-ITX remains unchanged
TEST=Autoport generates output for the ASRock Z97E-ITX/ac
Change-Id: I94c0b35245624d1a68ab69332fe9a5c5abfc5310
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90054
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When a critical battery level is detected without a charger present,
the system must shutdown to protect the battery from deep discharge.
Previously, this was an immediate power-off with minimal feedback.
This patch improves the shutdown sequence by:
1. Adding trigger_critical_battery_shutdown() to encapsulate the
safety logic.
2. Providing visual feedback by setting the ChromeOS LED to Red
during early boot flow (at romstage) for user feedback..
3. Logging an ELOG_TYPE_LOW_BATTERY_INDICATOR event to the event log
for post-mortem analysis.
4. Introducing a 5-second delay before power-off to ensure UART
logs are flushed and the user can observe the LED alert.
The shutdown logic remains in ramstage to ensure the user is able to
see the low-battery notification before powering off the system.
TEST=Boot Bluey with battery < critical threshold and no charger:
- Observed LED turning Red.
- Observed "Critical battery level..." warning in serial log.
- System powered off after 5 seconds.
- Verified 'cbmem -l' showed the low battery event after next boot.
Change-Id: I52948eac87417bca895000cb10dbaa87bb6a9384
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90850
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, display_startup() is called near the end of mainboard_init.
If the system enters a low-power boot mode (such as low-battery or
off-mode charging), the function returns early, leaving the display
uninitialized.
Move display_startup() before the is_low_power_boot() check. This
ensures the display is ready to show user notifications, such as
battery status or charging icons, even when the rest of the
mainboard initialization is skipped.
TEST=Build and boot Google/Quartz.
Change-Id: Ibaa2b20d3ea1ca8548ea6ebf93efbc48cb7a6b95
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90968
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, the system does not explicitly distinguish between a low
battery boot with a charger and one without. This is critical for
deciding whether to allow the boot to proceed or to protect the
battery.
This patch:
1. Re-introduces LB_BOOT_MODE_LOW_BATTERY to represent a critical
battery state without a charger present.
2. Refactors set_boot_mode() to accommodate off-mode charging and
evaluating battery health (low-batter w/ or w/o charger present)..
TEST=Verified on Bluey:
- Boot with charger + low battery enters LOW_BATTERY_CHARGING.
- Boot without charger + low battery enters LOW_BATTERY..
- Boot with normal battery enters NORMAL mode.
Change-Id: I2c9fa7eb61d1bbd6f9379c81577aee53ab6a0761
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90849
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current LB_BOOT_MODE_LOW_BATTERY actually implies a state where the
battery is below the critical threshold but a charger is attached,
allowing the system to boot into a charging-only or limited state.
Update the enum name to LB_BOOT_MODE_LOW_BATTERY_CHARGING across
coreboot tables and libpayload to better reflect this hardware state.
Changes:
- Rename boot mode enums in commonlib and libpayload.
- Update bluey mainboard logic to use the more descriptive name.
- Refactor is_low_power_boot() to is_low_power_boot_with_charger()
to improve code readability.
- Ensure the charger-present condition is explicitly checked in
romstage when setting the boot mode.
TEST=Verify bluey boots into off-mode charging and low-battery
charging modes correctly.
Change-Id: I2478c7519c781a8b5af78445899b7f9bf412cf42
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
This patch moves the ChromeEC battery-low LED signaling from the
Panther Lake SoC romstage code to the Fatcat mainboard-specific
romstage.
By utilizing the platform_romstage_pre_mem() hook, we remove Google-
specific EC logic from the generic Intel SoC directory, adhering better
to the separation of concerns between SoC and Mainboard code.
- Implement platform_romstage_pre_mem() in google/fatcat.
- Remove redundant EC include and LED logic from Panther Lake SoC.
Change-Id: I09f7dd516f1a98cf99313db379cfbef5157c9869
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91000
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Introduce platform_romstage_pre_mem() and platform_romstage_post_mem()
as weak symbols in the x86 romstage cycle.
These hooks allow SoCs and mainboards to execute low-level setup or
instrumentation immediately before and after memory initialization
without modifying the core romstage.c flow.
- platform_romstage_pre_mem: Called before mainboard_romstage_entry.
- platform_romstage_post_mem: Called after memory is up but while still
running on the Cache-as-RAM (CAR) stack.
Change-Id: I59cb115de0d512106d9a029d683c10b025076893
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90999
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement google_chromeec_is_critically_low_on_battery() to check if
the system is at risk of an imminent power-off.
This function returns true only if the battery is below the critical
threshold and no charger is detected. Combining these checks into a
single helper ensures that firmware notifications (like a red
lightbar) or emergency power-down logic do not trigger while the
device is successfully connected to AC power.
- Implement google_chromeec_is_critically_low_on_battery in ec.c.
- Export the function in ec.h for use in romstage/ramstage.
TEST=Verified on Fatcat & Bluey that the function correctly identifies
the low-power state and suppresses warnings when a charger is plugged
in.
Change-Id: I9f0f268d6660d913f989a9deffa24ab1f585b508
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90963
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Display flickering and occasional corruption were observed during panel
initialization on some TM_TL121BVMS07_00C panels when using an EMI-type
FPC.
According to Ilitek, this is caused by insufficient RX margin under
higher EMI conditions. Increasing receiver EQ, mask, bias, and voltage
settings improves signal tolerance and stabilizes display output.
Update the panel initialization code with the following parameters:
EQ:
P6_8F = 0xF0
Mask:
P8_82 = 0x13
P8_7D = 0x84
P8_7F = 0xDA
Bias:
P6_90 = 0x55
Voltage:
P5_3F = 0x47
Datasheet: Preliminary+specification+TL121BVMS07+-00+V01+20250721.pdf
BUG=b:479436242
TEST=build and check firmware screen.
BRANCH=skywalker
Change-Id: Id8272103abfb94f4d4f4d915107eafb9d0f4edc9
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Define `BOOTMEDIA_SMM_BWP`, `BOOTMEDIA_SMM_PWP_RUNTIME_OPTION` and
`DRIVERS_EFI_FW_INFO` Kconfig type as bool to satisfy Kconfig lint
requirements.
TEST=None
Change-Id: Ie798378665e6bd3e00ce271e17b36e81df92e2ad
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
protection
Add support for runtime control of BIOS lock
(BOOTMEDIA_SMM_BWP) via the CFR option API. This allows
users to enable/disable BIOS write protection in SMM
through the setup menu when explicitly enabled.
The implementation adds a new "bios_lock" CFR option that:
- Controls SMM BIOS write protection at runtime
- Sets EISS (Enable InSMM.STS) when enabled
- Enables SPI/LPC write protection in SMM
- Prevents unauthorised BIOS modifications outside SMM
Security model:
- Runtime control is opt-in via
BOOTMEDIA_SMM_BWP_RUNTIME_OPTION config
- When disabled, the option is suppressed in CFR
(not exposed in UI)
- Compile-time CONFIG(BOOTMEDIA_SMM_BWP) serves as the
default/fallback
- Protects against unauthorised EFI variable
modifications, bypassing BIOS lock when the runtime
option is not enabled
The option is integrated into Intel's common lockdown
code and SMI handlers, replacing compile-time-only
checks with conditional runtime lookups where
BOOTMEDIA_SMM_BWP_RUNTIME_OPTION is enabled.
Change-Id: Ie3b63462501e0d204c33dc3f8a006b73da0899d3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89919
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the ModPHY settings are also available on other Intel platforms,
these parameters should be moved to common code.
Change-Id: Ic2666c7bbd576681dea7f360c396c068b42306e2
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90943
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Using this, the compiler is going to check if the printf formatting is
correct for our printk messages.
Since we already have the macro, might as well use it.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I247f24ed64c2be7fc411f5e2fdd38715698bc4e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90829
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 55a972236e ("chromeec: Disable battery remaining capacity
workaround") disabled the workaround for all ChromeEC devices, since
newer EC firmware applies compensation via battery_compensate_params.
Older boards use EC branches that lack this logic; without it, users can
see 93–100% charge–discharge cycling and stale full-capacity reporting.
Add a Kconfig to configure the workaround, and select it for older
boards whose EC firmware lacks battery_compensate_params logic.
EC firmware branches were inspected to determine which ones lack this
logic.
TEST=build/boot google/lulu, verify battery full indication works
correctly with the Kconfig selected.
Change-Id: I096e0cf402e07f846b961319e01fb8f2c2dde7fc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90960
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
In the first boot after coreboot is flashed, ABL FW performs
memory training and passes APOB data to coreboot. coreboot
writes APOB data in SPI flash along with hash of the APOB data.
If APOB signature is not written in CMOS, Memory context is
not restored by ABL in subsequent boot and full training is
initiated which increases boot time.coreboot keeps writing the
APOB data to flash in every boot due to hash mismatch of APOB
data which inturn increases boot time.This change fixes the
issue of ABL FW not doing Memory Context restore due to missing
CMOS signature.On some older platforms FSP writes this signature
unconditionally and hence this coreboot patch doesnt impact
the older platforms.
TEST= Validated on crater platform. APOB write is not initiated
by coreboot on every boot. APOB write to flash happens only once
after the coreboot flash.
Change-Id: Id799d0d2ed9f54e29db7681509f3d66c1638b6ac
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90947
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes logo_valignment from overridetree.cb. The alignment
`FW_SPLASH_VALIGNMENT_CENTER` is the default behavior in the coreboot
splash driver, making this explicit assignment unnecessary.
BUG=none
TEST=Build and boot lapis; verify logo remains centered.
Change-Id: Ibf3ea2a9843b31f39fd08621f6056e63c2676ff7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90965
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Fix regression introduced by commit d18cc50e6a ("soc/intel/xeon_sp:
Use common smm_relocate").
The MSR SMM_FEATURE_CONTROL_MSR is only implemented on client SoCs.
Starting from Haswell server onwards the "SMM feature control" on
server platforms resides on the UBOX in PCI space.
Parallel SMM relocation was never supported on server platforms, thus
disable parallel SMM relocation for now and thus fix booting on all
Xeon-SP platforms. Added a FIXME to possibly implement this feature
in the future.
TEST=Can boot on OCP/tiogapass again.
Change-Id: I7b4fbe633046acbf9f921cca722ff343a64962cd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This reverts commit 60c8496afe.
The reason for needing that was the EC initialising PM1DO to 0
on reset, which set the OBF flag, leading to coreboot consuming
0 on it's first read.
This issue has now been fixed, so the rety is no longer needed.
Change-Id: I87b779e3859daecfe6285cd499e8d6b61cdbb852
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90979
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Don't print leftover devices when they are disabled in the devicetree.
It's expected to not find a device when it's not enabled.
Change-Id: Ia6e998d3088fbd329f976e66a92e08ecae9f760a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The generic Intel SMM S5 entry path disables all GPEs before asserting
SLP_EN, which clears OS-armed wake enables (e.g. LAN_WAKE) and prevents
Wake-on-LAN from S5.
Add a mainboard override hook, mainboard_smi_sleep_finalize(), called
after the S5 teardown but before SLP_EN is asserted, allowing boards to
restore required wake sources.
Change-Id: I9e97308ed94961fc4c08a10714b1b53f198bb593
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Rather than separate devicetrees for each variant, convert to using a
single baseboard devicetree plus overridetrees for each variant.
The Reef uses variant uses the baseboard only (no override).
- Set DEVICETREE to variants/baseboard/devicetree.cb for all variants
- Add OVERRIDE_DEVICETREE for non-reef variants
- Add overridetree.cb for coral, sand, pyro, snappy with only the
differences from the baseboard
- Remove variant devicetree.cb files
TEST=build all REEF variants
Change-Id: I1e8edc968cb0a733b23007dc2295b7f1189ea4fa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90928
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Convert all PCI device and USB port references in the reef devicetrees
to use aliases from the Apollolake chipset.cb instead of direct device/
function numbers. This improves maintainability by using symbolic
names, and reduces file size by eliminating entries which match those
in the chipset devicetree.
TEST=Build all reef variants
Change-Id: I08f96d2367fa8fc1ac7eb785c0d5cc08e293921b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90927
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Convert all PCI device and USB port references in octopus baseboard
devicetree and variant overridetrees to use aliases from the Geminilake
chipset.cb instead of direct device/function numbers. This improves
maintainability by using symbolic names, and reduces file size by
eliminating entries which match those in the chipset or baseboard
devicetrees.
TEST=Build all octopus variants
Change-Id: Ic4f93608234b52d548d8e5f94b137754e8924484
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
It's selected at the SoC level now, so no need for the mainboard to
select it as well.
TEST=build octopus
Change-Id: Id8bf73de73fd9c93e875c52b339b63970c32d50a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add USB port aliases to chipset_glk.cb and chipset_apl.cb to enable
boards to use device ref syntax for USB devices. Port counts match
hardware specs: GLK has 9 USB2/7 USB3 ports, APL has 8 USB2/7 USB3
ports.
Select 'DRIVERS_USB_ACPI' so that the required USB ACPI drivers are
built and linked for all boards.
Change-Id: Ibc7dd2cbfda8c8eb42b243ea7adcdb6d1fdea98b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Select SOC_INTEL_COMMON_BLOCK_ASPM and use the SoC common code for
programming PCIe root port power management. This adds programming of
PCIe RP clock PM and port speed, as well as allows for user override
via setup options for all fields. Remove the now-unused static methods
get_l1_substate_control() and get_aspm_control().
Additionally, check the port enable status before declaring the root
port config struct, to be consistent with ADL and MTL.
Change-Id: Ic30d714e609612ea46d34252c7c1d799652a9c2b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90879
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move SDXC device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from sd.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
SDXC controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: Ifee16988d0e5625a7b3c2be51ab70d2c8471747a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Move CNVI WiFi device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them.
Remove corresponding DIDs from cnvi.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
Remove the static declaration from cnvi_wifi_ops so the symbol is
exported and visible outside of cnvi.c.
This standardizes the approach across Intel SoCs and makes the
CNVI WiFi controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: I82a2b20a8b967d1a3d5a80ae477def260c366be7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90922
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move XDCI device operations linking from PCI Device ID matching
to chipset.cb files for all Intel SoCs that have them, matching the
approach used by Skylake.
Remove corresponding DIDs from xdci.c for these SoCs; keep DID
matching only for SoCs without chipset.cb files.
This standardizes the approach across Intel SoCs and makes the
XDCI controller configuration explicit in devicetree, and prevents
the endless proliferation of DIDs in the common driver code.
Change-Id: Ie8f8b5a952d072ecd1721bc8537734e85769b09d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
