mb/starlabs/byte_adl: Allow WOL in S5

Utilise mainboard_smi_sleep_finalize to leave LAN_WAKE# armed
when entering S5.

Change-Id: I85d3bea71f07dae1c9d6caa89015d52dca5116ce
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit is contained in:
Sean Rhodes 2026-01-18 21:20:33 +00:00
commit 7c4a0479dd
2 changed files with 29 additions and 2 deletions

View file

@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <arch/io.h>
#include <cpu/x86/smm.h>
#include <intelblocks/pmclib.h>
#include <soc/gpe.h>
#include <soc/iomap.h>
#include <soc/pm.h>
#include <types.h>
void mainboard_smi_sleep_finalize(u8 slp_typ)
{
if (slp_typ != ACPI_S5)
return;
/*
* Keep LAN_WAKE# armed in S5 for WOL.
* GPE0_LAN_WAK is GPE 112, which is bit 16 in the STD GPE block (127:96).
*/
const uint32_t lan_wake_mask = 1U << (GPE0_LAN_WAK - 96);
/* Clear any pending LAN_WAKE event to avoid immediate wake. */
outl(lan_wake_mask, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD));
pmc_enable_std_gpe(lan_wake_mask);
outl(lan_wake_mask, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD));
}

View file

@ -156,7 +156,7 @@ chip soc/intel/alderlake
}"
chip drivers/pcie/generic
register "wake_gpe" = "GPE0_LAN_WAK"
register "wake_deepest" = "ACPI_S3"
register "wake_deepest" = "ACPI_S5"
device generic 0 on end
end
smbios_slot_desc "SlotTypePciExpressGen4x1"
@ -174,7 +174,7 @@ chip soc/intel/alderlake
}"
chip drivers/pcie/generic
register "wake_gpe" = "GPE0_LAN_WAK"
register "wake_deepest" = "ACPI_S3"
register "wake_deepest" = "ACPI_S5"
device generic 0 on end
end
smbios_slot_desc "SlotTypePciExpressGen3X4"