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mb/google/reef: Convert to use variant overridetrees

Browse source 
Rather than separate devicetrees for each variant, convert to using a
single baseboard devicetree plus overridetrees for each variant.
The Reef uses variant uses the baseboard only (no override).

- Set DEVICETREE to variants/baseboard/devicetree.cb for all variants
- Add OVERRIDE_DEVICETREE for non-reef variants
- Add overridetree.cb for coral, sand, pyro, snappy with only the
  differences from the baseboard
- Remove variant devicetree.cb files

TEST=build all REEF variants

Change-Id: I1e8edc968cb0a733b23007dc2295b7f1189ea4fa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90928
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier 2026-01-26 12:27:04 -06:00 • committed by Sean Rhodes
commit 2bccc76db6
9 changed files with 290 additions and 981 deletions
Download patch file Download diff file Expand all files Collapse all files

7
src/mainboard/google/reef/Kconfig
View file

@ -76,12 +76,11 @@ config VARIANT_DIR
default "coral" if BOARD_GOOGLE_CORAL
config DEVICETREE
default "variants/coral/devicetree.cb" if BOARD_GOOGLE_CORAL
default "variants/pyro/devicetree.cb" if BOARD_GOOGLE_PYRO
default "variants/sand/devicetree.cb" if BOARD_GOOGLE_SAND
default "variants/snappy/devicetree.cb" if BOARD_GOOGLE_SNAPPY
default "variants/baseboard/devicetree.cb"
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_REEF
config MAINBOARD_PART_NUMBER
default "Reef" if BOARD_GOOGLE_REEF
default "Pyro" if BOARD_GOOGLE_PYRO

242
src/mainboard/google/reef/variants/coral/devicetree.cb
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@ -1,242 +0,0 @@
chip soc/intel/apollolake
register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports
register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
register "prt0_gpio" = "GPIO_122"
# GPIO for SD card detect
register "sdcard_cd_gpio" = "GPIO_177"
# EMMC TX DATA Delay 1
# Refer to EDS-Vol2-22.3.
# [14:8] steps of delay for HS400, each 125ps.
# [6:0] steps of delay for SDR104/HS200, each 125ps.
register "emmc_tx_data_cntl1" = "0x0C16"
# EMMC TX DATA Delay 2
# Refer to EDS-Vol2-22.3.
# [30:24] steps of delay for SDR50, each 125ps.
# [22:16] steps of delay for DDR50, each 125ps.
# [14:8] steps of delay for SDR25/HS50, each 125ps.
# [6:0] steps of delay for SDR12, each 125ps.
register "emmc_tx_data_cntl2" = "0x28162828"
# EMMC RX CMD/DATA Delay 1
# Refer to EDS-Vol2-22.3.
# [30:24] steps of delay for SDR50, each 125ps.
# [22:16] steps of delay for DDR50, each 125ps.
# [14:8] steps of delay for SDR25/HS50, each 125ps.
# [6:0] steps of delay for SDR12, each 125ps.
register "emmc_rx_cmd_data_cntl1" = "0x00181717"
# EMMC RX CMD/DATA Delay 2
# Refer to EDS-Vol2-22.3.
# [17:16] stands for Rx Clock before Output Buffer
# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
# [6:0] steps of delay for HS200, each 125ps.
register "emmc_rx_cmd_data_cntl2" = "0x10008"
# Enable DPTF
register "dptf_enable" = "true"
# PL1 override 12 W: the energy calculation is wrong with the
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
# Set RAPL PL2 to 15W.
register "power_limits_config" = "{
.tdp_pl1_override = 12,
.tdp_pl2_override = 15,
}"
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"
register "hdaudio_pwr_gate_enable" = "1"
register "hdaudio_bios_config_lockdown" = "1"
# Enable lpss s0ix
register "lpss_s0ix_enable" = "true"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route, i.e., if this route changes then the affected GPE
# offset bits also need to be changed. This sets the PMC register
# GPE_CFG fields.
register "gpe0_dw1" = "PMC_GPE_N_31_0"
register "gpe0_dw2" = "PMC_GPE_N_63_32"
register "gpe0_dw3" = "PMC_GPE_SW_31_0"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | Audio |
#| I2C2 | TPM |
#| I2C3 | Touchscreen |
#| I2C4 | Trackpad |
#| I2C5 | Digitizer |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
},
.i2c[2] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 57,
.fall_time_ns = 28,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 114,
.fall_time_ns = 164,
.data_hold_time_ns = 350,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 152,
.fall_time_ns = 30,
},
}"
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"
device domain 0 on
device ref igd on
register "gfx" = "GMA_DEFAULT_PANEL(0)"
end
device ref p2sb on end
device ref pmc on end
device ref fast_spi on end
device ref sram on end
device ref hda on
chip drivers/generic/max98357a
register "hid" = ""MX98357A""
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
register "sdmode_delay" = "5"
device generic 0 on end
end
end
device ref heci1 on end
device ref heci2 on end
device ref heci3 on end
device ref pcie_rp05 on
chip drivers/wifi/generic
register "wake" = "GPE0_DW3_00"
device pci 00.0 on end
end
end
device ref xhci on end
device ref i2c0 on
chip drivers/i2c/da7219
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
register "btn_cfg" = "50"
register "mic_det_thr" = "200"
register "jack_ins_deb" = "20"
register "jack_det_rate" = ""32ms_64ms""
register "jack_rem_deb" = "1"
register "a_d_btn_thr" = "0xa"
register "d_b_btn_thr" = "0x16"
register "b_c_btn_thr" = "0x21"
register "c_mic_btn_thr" = "0x3e"
register "btn_avg" = "4"
register "adc_1bit_rpt" = "1"
register "micbias_lvl" = "2600"
register "mic_amp_in_sel" = ""diff""
device i2c 1a on end
end
end
device ref i2c1 on end
device ref i2c2 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
device i2c 50 on end
end
end
device ref i2c3 on
chip drivers/i2c/generic
register "hid" = ""ELAN0001""
register "desc" = ""ELAN Touchscreen""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "detect" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "reset_delay_ms" = "20"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "enable_delay_ms" = "1"
register "has_power_resource" = "true"
device i2c 10 on end
end
chip drivers/i2c/generic
register "hid" = ""RAYD0001""
register "desc" = ""Raydium Touchscreen""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "detect" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "reset_delay_ms" = "1"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "enable_delay_ms" = "50"
register "has_power_resource" = "true"
device i2c 39 on end
end
end
device ref i2c4 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
register "wake" = "GPE0_DW1_15"
register "detect" = "1"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""SYNA0000""
register "generic.cid" = ""ACPI0C50""
register "generic.desc" = ""Synaptics Touchpad""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
register "generic.wake" = "GPE0_DW1_15"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x20"
device i2c 0x2c on end
end
end
device ref i2c5 on
chip drivers/i2c/hid
register "generic.hid" = ""WCOM50C1""
register "generic.desc" = ""WCOM Digitizer""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_13_IRQ)"
register "hid_desc_reg_offset" = "0x1"
device i2c 0x9 on end
end
end
device ref uart0 on end
device ref uart1 off end
device ref uart2 off end
device ref spi0 on end
device ref pwm on end
device ref sdcard on end
device ref emmc on end
device ref lpc_espi on
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end
device ref smbus on end
end
end

52
src/mainboard/google/reef/variants/coral/overridetree.cb Normal file
View file

@ -0,0 +1,52 @@
chip soc/intel/apollolake
device domain 0 on
device ref i2c3 on
chip drivers/i2c/generic
register "hid" = ""ELAN0001""
register "desc" = ""ELAN Touchscreen""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "detect" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "reset_delay_ms" = "20"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "enable_delay_ms" = "1"
register "has_power_resource" = "true"
device i2c 10 on end
end
chip drivers/i2c/generic
register "hid" = ""RAYD0001""
register "desc" = ""Raydium Touchscreen""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "detect" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "reset_delay_ms" = "1"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "enable_delay_ms" = "50"
register "has_power_resource" = "true"
device i2c 39 on end
end
end
device ref i2c4 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
register "wake" = "GPE0_DW1_15"
register "detect" = "1"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""SYNA0000""
register "generic.cid" = ""ACPI0C50""
register "generic.desc" = ""Synaptics Touchpad""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
register "generic.wake" = "GPE0_DW1_15"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x20"
device i2c 0x2c on end
end
end
device ref uart1 off end
device ref uart2 off end
end
end

235
src/mainboard/google/reef/variants/pyro/devicetree.cb
View file

@ -1,235 +0,0 @@
chip soc/intel/apollolake
register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports
register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
register "prt0_gpio" = "GPIO_122"
# GPIO for SD card detect
register "sdcard_cd_gpio" = "GPIO_177"
# EMMC TX DATA Delay 1
# Refer to EDS-Vol2-22.3.
# [14:8] steps of delay for HS400, each 125ps.
# [6:0] steps of delay for SDR104/HS200, each 125ps.
register "emmc_tx_data_cntl1" = "0x0C16"
# EMMC TX DATA Delay 2
# Refer to EDS-Vol2-22.3.
# [30:24] steps of delay for SDR50, each 125ps.
# [22:16] steps of delay for DDR50, each 125ps.
# [14:8] steps of delay for SDR25/HS50, each 125ps.
# [6:0] steps of delay for SDR12, each 125ps.
register "emmc_tx_data_cntl2" = "0x28162828"
# EMMC RX CMD/DATA Delay 1
# Refer to EDS-Vol2-22.3.
# [30:24] steps of delay for SDR50, each 125ps.
# [22:16] steps of delay for DDR50, each 125ps.
# [14:8] steps of delay for SDR25/HS50, each 125ps.
# [6:0] steps of delay for SDR12, each 125ps.
register "emmc_rx_cmd_data_cntl1" = "0x00181717"
# EMMC RX CMD/DATA Delay 2
# Refer to EDS-Vol2-22.3.
# [17:16] stands for Rx Clock before Output Buffer
# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
# [6:0] steps of delay for HS200, each 125ps.
register "emmc_rx_cmd_data_cntl2" = "0x10008"
# Enable DPTF
register "dptf_enable" = "true"
# PL1 override 12 W: the energy calculation is wrong with the
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
# Set RAPL PL2 to 15W.
register "power_limits_config" = "{
.tdp_pl1_override = 12,
.tdp_pl2_override = 15,
}"
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"
register "hdaudio_pwr_gate_enable" = "1"
register "hdaudio_bios_config_lockdown" = "1"
# Enable lpss s0ix
register "lpss_s0ix_enable" = "true"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route, i.e., if this route changes then the affected GPE
# offset bits also need to be changed. This sets the PMC register
# GPE_CFG fields.
register "gpe0_dw1" = "PMC_GPE_N_31_0"
register "gpe0_dw2" = "PMC_GPE_N_63_32"
register "gpe0_dw3" = "PMC_GPE_SW_31_0"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | Audio |
#| I2C2 | TPM |
#| I2C3 | Touchscreen |
#| I2C4 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
},
.i2c[2] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 50,
.fall_time_ns = 23,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 90,
.fall_time_ns = 164,
},
}"
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"
# Override USB2 PER PORT register (PORT 0)
register "usb2eye[0]" = "{
.Usb20PerPortPeTxiSet = 7,
.Usb20PerPortTxiSet = 1,
.Usb20IUsbTxEmphasisEn = 3,
.Usb20PerPortTxPeHalf = 0,
}"
# Override USB2 PER PORT register (PORT 1)
register "usb2eye[1]" = "{
.Usb20PerPortPeTxiSet = 7,
.Usb20PerPortTxiSet = 2,
.Usb20IUsbTxEmphasisEn = 3,
.Usb20PerPortTxPeHalf = 0,
}"
device domain 0 on
device ref igd on
register "gfx" = "GMA_DEFAULT_PANEL(0)"
end
device ref p2sb on end
device ref pmc on end
device ref fast_spi on end
device ref sram on end
device ref hda on
chip drivers/generic/max98357a
register "hid" = ""MX98357A""
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
register "sdmode_delay" = "5"
device generic 0 on end
end
end
device ref heci1 on end
device ref heci2 on end
device ref heci3 on end
device ref pcie_rp05 on
chip drivers/wifi/generic
register "wake" = "GPE0_DW3_00"
device pci 00.0 on end
end
end
device ref xhci on end
device ref i2c0 on
chip drivers/i2c/da7219
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
register "btn_cfg" = "50"
register "mic_det_thr" = "200"
register "jack_ins_deb" = "20"
register "jack_det_rate" = ""32ms_64ms""
register "jack_rem_deb" = "1"
register "a_d_btn_thr" = "0xa"
register "d_b_btn_thr" = "0x16"
register "b_c_btn_thr" = "0x21"
register "c_mic_btn_thr" = "0x3e"
register "btn_avg" = "4"
register "adc_1bit_rpt" = "1"
register "micbias_lvl" = "2600"
register "mic_amp_in_sel" = ""diff""
device i2c 1a on end
end
end
device ref i2c1 on end
device ref i2c2 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
device i2c 50 on end
end
end
device ref i2c3 on
chip drivers/i2c/hid
register "generic.hid" = ""WCOMNTN2""
register "generic.desc" = ""WCOM Touchscreen""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "generic.detect" = "1"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "generic.reset_delay_ms" = "20"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "generic.enable_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x1"
device i2c 0xA on end
end
chip drivers/i2c/generic
register "hid" = ""ELAN0001""
register "desc" = ""ELAN Touchscreen""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "detect" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "reset_delay_ms" = "20"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "enable_delay_ms" = "1"
register "has_power_resource" = "true"
device i2c 10 on end
end
end
device ref i2c4 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
register "wake" = "GPE0_DW1_15"
register "detect" = "1"
device i2c 15 on end
end
end
device ref i2c5 off end
device ref i2c6 off end
device ref uart0 on end
device ref uart1 on end
device ref uart2 on end
device ref spi0 on end
device ref pwm on end
device ref sdcard on end
device ref emmc on end
device ref lpc_espi on
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end
device ref smbus on end
end
end

74
src/mainboard/google/reef/variants/pyro/overridetree.cb Normal file
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@ -0,0 +1,74 @@
chip soc/intel/apollolake
# Intel Common SoC Config (no i2c[5])
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
},
.i2c[2] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 50,
.fall_time_ns = 23,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 90,
.fall_time_ns = 164,
},
}"
# Override USB2 PER PORT register (PORT 0)
register "usb2eye[0]" = "{
.Usb20PerPortPeTxiSet = 7,
.Usb20PerPortTxiSet = 1,
.Usb20IUsbTxEmphasisEn = 3,
.Usb20PerPortTxPeHalf = 0,
}"
# Override USB2 PER PORT register (PORT 1)
register "usb2eye[1]" = "{
.Usb20PerPortPeTxiSet = 7,
.Usb20PerPortTxiSet = 2,
.Usb20IUsbTxEmphasisEn = 3,
.Usb20PerPortTxPeHalf = 0,
}"
device domain 0 on
device ref i2c3 on
chip drivers/i2c/hid
register "generic.hid" = ""WCOMNTN2""
register "generic.desc" = ""WCOM Touchscreen""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "generic.detect" = "1"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "generic.reset_delay_ms" = "20"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "generic.enable_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x1"
device i2c 0xA on end
end
chip drivers/i2c/generic
register "hid" = ""ELAN0001""
register "desc" = ""ELAN Touchscreen""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "detect" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "reset_delay_ms" = "20"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "enable_delay_ms" = "1"
register "has_power_resource" = "true"
device i2c 10 on end
end
end
device ref i2c5 off end
device ref i2c6 off end
end
end

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chip soc/intel/apollolake
register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports
register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
register "prt0_gpio" = "GPIO_122"
# EMMC TX DATA Delay 1
# Refer to EDS-Vol2-22.3.
# [14:8] steps of delay for HS400, each 125ps.
# [6:0] steps of delay for SDR104/HS200, each 125ps.
register "emmc_tx_data_cntl1" = "0x0C16"
# EMMC TX DATA Delay 2
# Refer to EDS-Vol2-22.3.
# [30:24] steps of delay for SDR50, each 125ps.
# [22:16] steps of delay for DDR50, each 125ps.
# [14:8] steps of delay for SDR25/HS50, each 125ps.
# [6:0] steps of delay for SDR12, each 125ps.
register "emmc_tx_data_cntl2" = "0x28162828"
# EMMC RX CMD/DATA Delay 1
# Refer to EDS-Vol2-22.3.
# [30:24] steps of delay for SDR50, each 125ps.
# [22:16] steps of delay for DDR50, each 125ps.
# [14:8] steps of delay for SDR25/HS50, each 125ps.
# [6:0] steps of delay for SDR12, each 125ps.
register "emmc_rx_cmd_data_cntl1" = "0x00181717"
# EMMC RX CMD/DATA Delay 2
# Refer to EDS-Vol2-22.3.
# [17:16] stands for Rx Clock before Output Buffer
# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
# [6:0] steps of delay for HS200, each 125ps.
register "emmc_rx_cmd_data_cntl2" = "0x10008"
# Enable DPTF
register "dptf_enable" = "true"
# PL1 override 12 W: the energy calculation is wrong with the
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
# Set RAPL PL2 to 15W.
register "power_limits_config" = "{
.tdp_pl1_override = 12,
.tdp_pl2_override = 15,
}"
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"
register "hdaudio_pwr_gate_enable" = "1"
register "hdaudio_bios_config_lockdown" = "1"
# Enable lpss s0ix
register "lpss_s0ix_enable" = "true"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route, i.e., if this route changes then the affected GPE
# offset bits also need to be changed. This sets the PMC register
# GPE_CFG fields.
register "gpe0_dw1" = "PMC_GPE_N_31_0"
register "gpe0_dw2" = "PMC_GPE_N_63_32"
register "gpe0_dw3" = "PMC_GPE_SW_31_0"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | Audio |
#| I2C2 | TPM |
#| I2C3 | Touchscreen |
#| I2C4 | Trackpad |
#| I2C5 | Digitizer |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
},
.i2c[2] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 57,
.fall_time_ns = 28,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 114,
.fall_time_ns = 164,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 152,
.fall_time_ns = 30,
},
}"
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"
device domain 0 on
device ref igd on
register "gfx" = "GMA_DEFAULT_PANEL(0)"
end
device ref p2sb on end
device ref pmc on end
device ref fast_spi on end
device ref sram on end
device ref hda on
chip drivers/generic/max98357a
register "hid" = ""MX98357A""
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
register "sdmode_delay" = "5"
device generic 0 on end
end
end
device ref heci1 on end
device ref heci2 on end
device ref heci3 on end
device ref pcie_rp05 on
chip drivers/wifi/generic
register "wake" = "GPE0_DW3_00"
device pci 00.0 on end
end
end
device ref xhci on end
device ref i2c0 on
chip drivers/i2c/da7219
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
register "btn_cfg" = "50"
register "mic_det_thr" = "200"
register "jack_ins_deb" = "20"
register "jack_det_rate" = ""32ms_64ms""
register "jack_rem_deb" = "1"
register "a_d_btn_thr" = "0xa"
register "d_b_btn_thr" = "0x16"
register "b_c_btn_thr" = "0x21"
register "c_mic_btn_thr" = "0x3e"
register "btn_avg" = "4"
register "adc_1bit_rpt" = "1"
register "micbias_lvl" = "2600"
register "mic_amp_in_sel" = ""diff""
device i2c 1a on end
end
end
device ref i2c1 on end
device ref i2c2 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
device i2c 50 on end
end
end
device ref i2c3 on
chip drivers/i2c/generic
register "hid" = ""RAYD0001""
register "desc" = ""Raydium Touchscreen""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "detect" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "reset_delay_ms" = "20"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "enable_delay_ms" = "1"
register "has_power_resource" = "true"
device i2c 39 on end
end
end
device ref i2c4 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
register "wake" = "GPE0_DW1_15"
register "detect" = "1"
device i2c 15 on end
end
end
device ref i2c5 on
chip drivers/i2c/hid
register "generic.hid" = ""WCOM50C1""
register "generic.desc" = ""WCOM Digitizer""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_13_IRQ)"
register "hid_desc_reg_offset" = "0x1"
device i2c 0x9 on end
end
end
device ref uart0 on end
device ref uart1 on end
device ref uart2 on end
device ref spi0 on end
device ref pwm on end
device ref sdcard on end
device ref emmc on end
device ref lpc_espi on
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end
device ref smbus on end
end
end

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chip soc/intel/apollolake
# Intel Common SoC Config (i2c[4] without data_hold_time_ns)
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 104,
.fall_time_ns = 52,
},
.i2c[2] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 57,
.fall_time_ns = 28,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 76,
.fall_time_ns = 164,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 114,
.fall_time_ns = 164,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 152,
.fall_time_ns = 30,
},
}"
device domain 0 on
device ref i2c3 on
chip drivers/i2c/generic
register "hid" = ""RAYD0001""
register "desc" = ""Raydium Touchscreen""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "detect" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "reset_delay_ms" = "20"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "enable_delay_ms" = "1"
register "has_power_resource" = "true"
device i2c 39 on end
end
end
end
end

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chip soc/intel/apollolake
register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt
# Disable unused clkreq of PCIe root ports
register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# GPIO for PERST_0
# If the Board has PERST_0 signal, assign the GPIO
# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
register "prt0_gpio" = "GPIO_122"
# GPIO for SD card detect
register "sdcard_cd_gpio" = "GPIO_177"
# EMMC TX DATA Delay 1
# Refer to EDS-Vol2-22.3.
# [14:8] steps of delay for HS400, each 125ps.
# [6:0] steps of delay for SDR104/HS200, each 125ps.
register "emmc_tx_data_cntl1" = "0x0C16"
# EMMC TX DATA Delay 2
# Refer to EDS-Vol2-22.3.
# [30:24] steps of delay for SDR50, each 125ps.
# [22:16] steps of delay for DDR50, each 125ps.
# [14:8] steps of delay for SDR25/HS50, each 125ps.
# [6:0] steps of delay for SDR12, each 125ps.
register "emmc_tx_data_cntl2" = "0x28162828"
# EMMC RX CMD/DATA Delay 1
# Refer to EDS-Vol2-22.3.
# [30:24] steps of delay for SDR50, each 125ps.
# [22:16] steps of delay for DDR50, each 125ps.
# [14:8] steps of delay for SDR25/HS50, each 125ps.
# [6:0] steps of delay for SDR12, each 125ps.
register "emmc_rx_cmd_data_cntl1" = "0x00181717"
# EMMC RX CMD/DATA Delay 2
# Refer to EDS-Vol2-22.3.
# [17:16] stands for Rx Clock before Output Buffer
# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
# [6:0] steps of delay for HS200, each 125ps.
register "emmc_rx_cmd_data_cntl2" = "0x10008"
# Enable DPTF
register "dptf_enable" = "true"
# PL1 override 12 W: the energy calculation is wrong with the
# current VR solution. Experiments show that SoC TDP max (6W) can
# be reached when RAPL PL1 is set to 12W.
# Set RAPL PL2 to 15W.
register "power_limits_config" = "{
.tdp_pl1_override = 12,
.tdp_pl2_override = 15,
}"
# Enable Audio Clock and Power gating
register "hdaudio_clk_gate_enable" = "1"
register "hdaudio_pwr_gate_enable" = "1"
register "hdaudio_bios_config_lockdown" = "1"
# Enable lpss s0ix
register "lpss_s0ix_enable" = "true"
# GPE configuration
# Note that GPE events called out in ASL code rely on this
# route, i.e., if this route changes then the affected GPE
# offset bits also need to be changed. This sets the PMC register
# GPE_CFG fields.
register "gpe0_dw1" = "PMC_GPE_N_31_0"
register "gpe0_dw2" = "PMC_GPE_N_63_32"
register "gpe0_dw3" = "PMC_GPE_SW_31_0"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | Audio |
#| I2C2 | TPM |
#| I2C3 | Touchscreen |
#| I2C4 | Trackpad |
#| I2C5 | Digitizer |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 44,
.fall_time_ns = 22,
},
.i2c[2] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 40,
.fall_time_ns = 20,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 70,
.fall_time_ns = 164,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 20,
.fall_time_ns = 164,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 152,
.fall_time_ns = 30,
},
}"
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"
# Override USB2 PER PORT register (PORT 1)
register "usb2eye[1]" = "{
.Usb20PerPortPeTxiSet = 7,
.Usb20PerPortTxiSet = 0,
}"
device domain 0 on
device ref igd on
register "gfx" = "GMA_DEFAULT_PANEL(0)"
end
device ref p2sb on end
device ref pmc on end
device ref fast_spi on end
device ref sram on end
device ref hda on
chip drivers/generic/max98357a
register "hid" = ""MX98357A""
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
register "sdmode_delay" = "5"
device generic 0 on end
end
end
device ref heci1 on end
device ref heci2 on end
device ref heci3 on end
device ref pcie_rp05 on
chip drivers/wifi/generic
register "wake" = "GPE0_DW3_00"
device pci 00.0 on end
end
end
device ref xhci on end
device ref i2c0 on
chip drivers/i2c/da7219
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"
register "btn_cfg" = "50"
register "mic_det_thr" = "200"
register "jack_ins_deb" = "20"
register "jack_det_rate" = ""32ms_64ms""
register "jack_rem_deb" = "1"
register "a_d_btn_thr" = "0xa"
register "d_b_btn_thr" = "0x16"
register "b_c_btn_thr" = "0x21"
register "c_mic_btn_thr" = "0x3e"
register "btn_avg" = "4"
register "adc_1bit_rpt" = "1"
register "micbias_lvl" = "2600"
register "mic_amp_in_sel" = ""diff""
device i2c 1a on end
end
end
device ref i2c1 on end
device ref i2c2 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"
device i2c 50 on end
end
end
device ref i2c3 on
chip drivers/i2c/generic
register "hid" = ""ELAN0001""
register "desc" = ""ELAN Touchscreen""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "detect" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "reset_delay_ms" = "20"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "enable_delay_ms" = "1"
register "has_power_resource" = "true"
device i2c 10 on end
end
chip drivers/i2c/generic
register "hid" = ""MLFS0000""
register "desc" = ""Melfas Touchscreen""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "detect" = "1"
# Melfas TS IC doesn't have reset pin design, current FW also not
# declare "ce-gpios" in ACPI _DSD to let Melfas TS driver to know
# "enable gpio#152 (VTSP) but because of kernel bug & Melfas TS driver
# is unable to separate clear power sequence path for certain
# TS IC (ex: MIT-410) and kernel will still obstain GPIO from _CRS
# by index "0" since no matched "gpio" in ACPI _DSD.
# coreboot needs to have "dummy pin" as workaround in order to let
# kernel driver grab "useless" GPIO to prevent Melfas TS driver cut
# power by driver itself.
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "reset_delay_ms" = "1"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "enable_delay_ms" = "5"
register "has_power_resource" = "true"
device i2c 34 on end
end
chip drivers/i2c/generic
register "hid" = ""RAYD0001""
register "desc" = ""Raydium Touchscreen""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "detect" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "reset_delay_ms" = "1"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "enable_delay_ms" = "50"
register "has_power_resource" = "true"
device i2c 39 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""WDHT0002""
register "generic.desc" = ""WDT Touchscreen""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "generic.detect" = "1"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "generic.reset_delay_ms" = "130"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "generic.enable_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x20"
device i2c 2c on end
end
chip drivers/i2c/hid
register "generic.hid" = ""GTCH7503""
register "generic.desc" = ""G2TOUCH Touchscreen""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "generic.detect" = "1"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "generic.reset_delay_ms" = "50"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "generic.enable_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 40 on end
end
end
device ref i2c4 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)"
register "wake" = "GPE0_DW1_15"
register "detect" = "1"
device i2c 15 on end
end
end
device ref i2c5 on
chip drivers/i2c/hid
register "generic.hid" = ""WCOM50C1""
register "generic.desc" = ""WCOM Digitizer""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_13_IRQ)"
register "hid_desc_reg_offset" = "0x1"
device i2c 0x9 on end
end
end
device ref uart0 on end
device ref uart1 on end
device ref uart2 on end
device ref spi0 on end
device ref pwm on end
device ref sdcard on end
device ref emmc on end
device ref lpc_espi on
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end
device ref smbus on end
end
end

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chip soc/intel/apollolake
# Intel Common SoC Config
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 44,
.fall_time_ns = 22,
},
.i2c[2] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 40,
.fall_time_ns = 20,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 70,
.fall_time_ns = 164,
},
.i2c[4] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 20,
.fall_time_ns = 164,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 152,
.fall_time_ns = 30,
},
}"
# Override USB2 PER PORT register (PORT 1)
register "usb2eye[1]" = "{
.Usb20PerPortPeTxiSet = 7,
.Usb20PerPortTxiSet = 0,
}"
device domain 0 on
device ref i2c3 on
chip drivers/i2c/generic
register "hid" = ""ELAN0001""
register "desc" = ""ELAN Touchscreen""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "detect" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "reset_delay_ms" = "20"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "enable_delay_ms" = "1"
register "has_power_resource" = "true"
device i2c 10 on end
end
chip drivers/i2c/generic
register "hid" = ""MLFS0000""
register "desc" = ""Melfas Touchscreen""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "detect" = "1"
# Melfas TS IC doesn't have reset pin design, current FW also not
# declare "ce-gpios" in ACPI _DSD to let Melfas TS driver to know
# "enable gpio#152 (VTSP) but because of kernel bug & Melfas TS driver
# is unable to separate clear power sequence path for certain
# TS IC (ex: MIT-410) and kernel will still obstain GPIO from _CRS
# by index "0" since no matched "gpio" in ACPI _DSD.
# coreboot needs to have "dummy pin" as workaround in order to let
# kernel driver grab "useless" GPIO to prevent Melfas TS driver cut
# power by driver itself.
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "reset_delay_ms" = "1"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "enable_delay_ms" = "5"
register "has_power_resource" = "true"
device i2c 34 on end
end
chip drivers/i2c/generic
register "hid" = ""RAYD0001""
register "desc" = ""Raydium Touchscreen""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "detect" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "reset_delay_ms" = "1"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "enable_delay_ms" = "50"
register "has_power_resource" = "true"
device i2c 39 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""WDHT0002""
register "generic.desc" = ""WDT Touchscreen""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "generic.detect" = "1"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "generic.reset_delay_ms" = "130"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "generic.enable_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x20"
device i2c 2c on end
end
chip drivers/i2c/hid
register "generic.hid" = ""GTCH7503""
register "generic.desc" = ""G2TOUCH Touchscreen""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)"
register "generic.detect" = "1"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"
register "generic.reset_delay_ms" = "50"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"
register "generic.enable_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 40 on end
end
end
end
end