This patch adds a new config option to limit the maximum DRAM
frequency for Pantherlake platforms.
The mainboard code should try to set `max_dram_speed_mts` from
override device tree if required.
BUG=b:373394046
TEST=Able to build and boot google/fatcat.
Change-Id: Ic92947b2997c116ea8ed0abff4c6b3c2ca956c65
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85101
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Brox mainboard does not reliably support S3 entry/exit. Hence do not
select HAVE_ACPI_RESUME config option. Also trigger a fail-safe board
reset if the system resumes from S3.
BUG=b:337274309
TEST=Build Brox BIOS image and boot to OS. Ensure that the _S3 name
variable is not advertised in the DSDT. Trigger a S3 entry and ensure
that on S3 exit, the board reset is triggered.
Change-Id: Ief0936fbcd9e5e34ef175736a858f98edf840719
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch optimizes the reset handling in the Alder Lake romstage while
disabling the UFS controller in an uni-boot scenario (a unified AP
firmware image can boot both UFS and non-UFS systems).
It introduces a check in `mainboard_expects_another_reset()` to skip
unnecessary resets when a CSE slot switch is due, meaning CSE is not
booting from the RW slot. This saves one reset for non-UFS SKUs when
a CSE slot switch is pending.
The patch also relocates the `cse_fw_sync()` call after disabling the
UFS controllers to ensure the system reset flow can be better optimized
and combined with any expected resets due to CSE synchronization.
TEST=Able to build google/trulo eMMC sku and able to save one reset.
Without this patch:
1. Warm reset after disabling UFS (1st reset)
2. Global reset after CSE sync (2nd reset)
3. Warm reset after disabling UFS (3rd reset)
4. Boot to OS
With this patch:
1. Skip disabling UFS if CSE sync is due, aka no reset.
2. Global reset after CSE sync (1st reset)
3. CSE is booting from slot RW meaning CSE sync is done, perform UFS
disabling and issue a warm reset after disabling UFS (2nd reset)
4. Boot to OS
Change-Id: I04e6943fb136d126a1d1a829aadb316d2cdd0ac9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Before entering FSP-M, AP firmware must ensure the PM1_CNT register
reflects the correct sleep state if a global reset occurred.
This is crucial when Intel CSE has reset the system, as indicated by
the global reset bit and wake status register.
If PM1_CNT doesn't contain a valid sleep state after a CSE reset, AP
firmware must enforce an S5 exit path before handing control to FSP-M
for CSE initialization. This ensures proper system initialization and
avoids potential issues caused by an inconsistent sleep state.
Additionally, clears the PM1 status register (PM1_STS) after retrieving
the power state. This prevents stale status information from persisting
across power cycles, which could lead to confusion during subsequent
boots.
BUG=b:265939425
TEST=Verified that `prev_sleep_state` holds the correct value
(5 for S5) after CSE performs a global reset.
Fixes: Inconsistent sleep state after CSE reset.
Change-Id: Iae9c026da86fef4a3571e06b1bb20504c3d8c9be
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch drops the X86_CLFLUSH_CAR config from the latest Intel SoCs
(ADL, MTL, PTL) following the switch to WC (Write-Combining) MTRR type
for the RAMTOP range.
Previously, with WB (Write-Back) caching for RAMTOP, CLFLUSH was
crucial to ensure data consistency, as WB caches both reads and writes.
However, since the RAMTOP range now relies on WC MTRR, the role of
CLFLUSH becomes less critical.
Removing CLFLUSH in this scenario can improve performance, as it avoids
unnecessary cache invalidations.
BUG=b:373290479
TEST=Able to build and boot google/trulo.
Change-Id: I3631a58ba03cd2fbe8821bc89b1ca7226c2f0fd4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85028
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Configuring the Early Caching Ramtop range as Write-Back (WB) before
memory initialization is NOT RECOMMENDED. Speculative execution within
this WB range can lead to issues. WB configuration should be applied
to this range ONLY AFTER memory initialization is complete.
To enable Ramtop caching before memory initialization, use
Write-Combining (WC) instead of Write-Back (WB).
This change applies the recommendation by always configuring the early
ramtop caching range as WC.
BUG=b:373290479
TEST=Able to build and boot google/trulo.
Change-Id: Idf6f0be1bc0daa8037ea9c52932eb72434156071
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85027
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This patch adds a new field, `size`, to the `ramtop_table` structure to
store the size of the RAMTOP region.
The RAMTOP size is calculated as the difference between the cbmem top
and the FSP reserved memory base address, aligned up to the nearest 4MB
boundary.
This change allows for more accurate tracking of the RAMTOP region and
improves compatibility with different memory configurations.
Previously, the RAMTOP size was always assumed to be 16MB. This could
lead to boot hangs on systems with different memory configurations,
where the actual RAMTOP size exceeded 16MB.
By dynamically calculating and storing the RAMTOP size, this patch
ensures that the correct memory range is used for intermediate
caching, preventing boot hangs and improving boot speed.
The `update_ramtop()` function is updated to write the calculated
RAMTOP size to CMOS along with the RAMTOP address.
The `early_ramtop_enable_cache_range()` function is also updated to
use the RAMTOP size from CMOS to set the correct MTRR range.
BUG=b:373290479
TEST=Built and booted successfully on various platforms. Verified that
the RAMTOP size is correctly calculated and stored in CMOS
Change-Id: I16d610c5791895b59da57d543c54da6621617912
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85003
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
The overall procedure is taken from the original code that was removed
in commit 4c38ed3c38 (cpu/via/nano: Drop support). Boilerplate at the
start and end was updated (expect timestamp and BIST result in `xmm*'
registers), stack is aligned to 16B, and linker symbols are now used
for the CAR and cached XIP ranges.
Change-Id: Ia190a3006fe897861b7b8a64d47e588871120dd1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82766
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Elan touchscreen override devicetree for rull based on the latest
schematic NB7559_MB_SCH_V1_2024_1010.pdf.
BUG=b:374629673
BRANCH=None
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. touchpanel function is normal and 'evtest' command displays the
touch point
Change-Id: Ie7f6dce0175c2940abfa14c4e407414912063112
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85015
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Map a proper DRAM range for memory test during calibration.
TEST=memory test passed on Rauru
BUG=b:317009620
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Change-Id: I06f31ef14715897ba889076d78b8c2d015dd08ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85035
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reduce stop delay for touchscreen based on the latest spec (EKTH6915
Product Spec_V1.0). This will optimize the touch response time to keep
the S0ix resume time under 500ms.
BUG=b:378012214
TEST=Verify improvement in resume time on Riven.
Change-Id: Id7dcbc393bfae9bb62b5700bb9042a543152e968
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85039
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I401e94b107612f8b7e8a73b3dbc12d7a5227ef01
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
As per commit 8651731537 ("sconfig: Move config_of_soc from device.h
to static.h") and commit 05a13e7ed9 ("sconfig: Move (WEAK_)DEV_PTR
from device.h to static.h"), sources that require access to the
devicetree should directly include static.h. This allows static.h to be
removed from device.h, eliminating many unnecessary dependencies on the
devicetree for objects that only need the device types and function
declarations.
Now that static.h has been included throughout the tree where necessary,
it can be removed from device.h.
Change-Id: Ie72840c71ffca2ada82456dda6a2c813f6a6c3ad
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84590
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
As per commit 8651731537 ("sconfig: Move config_of_soc from device.h
to static.h") and commit 05a13e7ed9 ("sconfig: Move (WEAK_)DEV_PTR
from device.h to static.h"), sources that use code generated from the
devicetree should directly include static.h. This allows static.h to be
removed from device.h, eliminating many unnecessary dependencies on the
devicetree for objects that only need the device types and function
declarations.
Add static.h to the includes of all remaining files that require static
devicetree access through config_of_soc(), the sconfig generated names,
or DEV_PTR().
Change-Id: I1d35ff2ac22f9ff5e0aa38b7ad707619e50387f3
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84591
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
As per commit 05a13e7ed9 ("sconfig: Move (WEAK_)DEV_PTR from device.h
to static.h"), sources that require access to devicetree static devices
should directly include static.h. This allows static.h to be removed
from device.h, eliminating unnecessary dependencies on the devicetree
for objects that only need the device types and function declarations.
The DEV_PTR macro resolves to names declared in static_devices.h, which
is then included in static.h, so include the header whenever the macro
is used.
Change-Id: I05662e601af00866b7f26f4c6c6794b491bf676e
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84678
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per commit 05a13e7ed9 ("sconfig: Move (WEAK_)DEV_PTR from device.h
to static.h"), sources that require access to devicetree static devices
should directly include static.h. This allows static.h to be removed
from device.h, eliminating unnecessary dependencies on the devicetree
for objects that only need the device types and function declarations.
The DEV_PTR macro resolves to names declared in static_devices.h, which
is then included in static.h, so include the header whenever the macro
is used.
Change-Id: Ie281e9a9c015b19bfc96b83021a6e3afd98abcc3
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84677
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Similar to commit 8651731537 ("sconfig: Move config_of_soc from
device.h to static.h"), move these macros to static.h to separate
dependencies on device.h and static.h. These macros resolve to device
alises that are declared in the generated static_devices.h header, so
move them to static.h which includes static_devices.h.
Since static.h remains included in device.h, any source that uses these
macros should still compile correctly. Subsequent commits will add
static.h to files that need them, after which static.h can be dropped
from device.h.
Change-Id: I1c76ad749769591da9c102b11eb618e93b68bd7c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84676
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
As per commit 8651731537 ("sconfig: Move config_of_soc from device.h
to static.h"), sources that require access to the devicetree should
directly include static.h so that it can be removed from device.h,
eliminating unnecessary dependencies on static.h for files that only
need the types and function declarations in device.h.
Change-Id: I3c118a707dfe7bb8932606f30eae52ef0b4c9efe
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
HPET General Capabilities and ID Register at offset 0x0 and Timer 0
Configuration and Capability Register at offset 0x100 are used to
determine the generation of HPET ACPI tables. This patch adds
macro definitions for these registers and fields. Definitions are
from IA-PC HPET (High Precision Event Timers) Specification Revision
1.0a.
Change-Id: I31413afcbfc42307e3ad3f99d75f33f87092d7aa
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84252
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel common IMC contains an embedded SMBus controller for SPD data
access. This patch implements IMC based SPD access supports through
MMIO.
Register definitons are from Intel Atom Processor C5100, C5300, P5300
and P5700 Product Families EDS, doc No. 575160 rev 2.0.
Change-Id: I3f47ddeda94d3882852d64c0052f8fb42b6b7ad2
Tested-by: Yuchi Chen <yuchi.chen@intel.com>
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
By default, PCH SMBus codes will be called to retrieve SPD data. This
patch adds a SPD IO layer so that SoC could implement its specific SPD
IO layer functions such as using Integrated Memory Controller to get
SPD data.
Change-Id: I656298aeda409fca3c85266b5b8727fac9bfc917
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84201
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel server processors have a different system agent design, it has
some differences with client platform such as (1) no BDSM and BGSM
registers; (2) different alignment size and bit fields in TOLUD,
TOUUD and TSEG registers. Thus this patch adds a new common block for
server platform system agent.
Change-Id: If32c2a6524c9d55ce7f9c3dd203bcf85cab76c2c
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83318
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support for the Integrated Sensor Hub (ISH) on the
Fatcat mainboard.
ISH can be enabled or disabled via FW_CONFIG bit 24. This allows for
flexible configuration depending on the system requirements.
The GPIO configuration for ISH is also updated based on CBI settings,
ensuring correct initialization and communication.
Verified that the device tree correctly probes ISH based on the
FW_CONFIG setting:
* FW_CONFIG with bit 24 set: ISH is probed successfully.
* FW_CONFIG with bit 24 cleared: ISH is not probed.
BUG=b:370984186
TEST=Verified ISH probing behavior with different FW_CONFIG settings
using CBI.
Change-Id: I1a9734139a49be982a7dd43d5afd92e7fea6b29c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This updates power_limits_config for Panther Lake U and H.
Source:
Intel PTL PDG 813278
Intel PTL FSP Power limit profiles table
BUG=b:357011633
TEST=Build fatcat and boot with Panther Lake SoC and RVP.
Change-Id: I1b9276af7f1e30b1cda3d8c016524fd6397fa4b2
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This patch adds new DID0 PCI device IDs for Intel PTL-H.
Additionally, updates the System Agent driver's `systemagent_ids`
list and Panther Lake SoC bootblock to support these new IDs.
Source: Intel PTL-FAS. Document Number 812562
BUG=b:347669091
TEST=Build fatcat and boot with Panther Lake SoC with newly added
MCH ID.
With patch, coreboot log:
`[DEBUG] MCH: device id b004 (rev 00) is Pantherlake H`
`[DEBUG] MCH: device id b00a (rev 00) is Pantherlake H`
Change-Id: I56e795696f661d88828d7549f856eee19c46c942
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84916
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Add SPI controller driver code with support for 8 buses (SPI0 to SPI7).
Test=Build pass, verify the wavefroms for SPI0~7 are correct.
BUG=b:317009620
Change-Id: I10dd1105931c4911ce5257803073b7af76115c75
Signed-off-by: Liya Li <ot_liya.li@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84930
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PLL and clock init code, frequency meter and APIs for raising
little CPU frequency and set tvdpll frequency.
TEST=build pass and driver init ok
BUG=b:317009620
Signed-off-by: Guangjie Song <guangjie.song@mediatek.corp-partner.google.com>
Change-Id: Icac99fb210c87c8b7b14af627fbd2f14e4c47240
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reduce stack usage of acpi_fill_srat_memory() by 18KiB.
Directly write the SRAT table entries instead of using a temporary
buffer on the stack.
FIXES: Crash on ocp/tiogapass when writing SRAT table
TEST: Still boots on intel/archercity_crb
Change-Id: I91a6787ade8b465da7837b241c0aab00251f7de4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84832
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When soc_acpi_name() returns NULL do not create the AML code.
This prevents errors on the OS side when it tries to parse the AML
code and doesn't find a name string for the device:
ACPI Warning: Invalid character(s) in name (0x44415F08), repaired: [*_AD]
Change-Id: I72225a975663a1028283437cac3b9231b7c77ead
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
In coreboot, LPC ACPI objects with its attached devices are
usually provided by static DSDT. For Xeon-SP Gen6 LPC, its logical
attached devices are created from dynamic SSDT (e.g. super IO).
Create a simple SSDT for LPC in dynamic way as well to complete
the device relationship chain.
Fix below issues during Linux OS boot. The issue will block
Windows OS boot as well.
[ 22.986142] ACPI BIOS Error (bug): Could not resolve symbol [\_SB.DI00.LPCB], AE_NOT_FOUND (20230628/dswload2-162)
[ 22.986792] ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20230628/psobject-220)
[ 22.987786] ACPI: Skipping parse of AML opcode: Scope (0x0010)
Change-Id: I08543fc77f0f3e633b05889e921c5183e6e20d8e
Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84842
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow the power team’s recommendation:
- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to SLEW_FAST_4
- Set FastPkgCRampDisable VCCIA and VCCGT to 1
BUG=b:376165743
TEST=built firmware and verified by power team,
the acoustic noise can be improved a lot.
Change-Id: Ia71985ef21d634763fc5ae22e4f611f7f5e9652a
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Realtek AX generation IC utilizes LTR-issued latency requests to
optimize WiFi latency and power consumption, it requires host
enabling LTR to meet the design requirement. We enabled the host's
LTR by enabling PCIe root port 8, which met resltek's technical
requirements.
BUG=b:377400590
TEST=Tested on Drawman with RTL8852BE
Use command $ lspci -vv, LTR+ is listed on DevCtl2
BRANCH=firmware-dedede-13606.B
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Change-Id: I093951f71e971fe83d61d9fcda8bf16cc5f82ffe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85011
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch addresses uninitialized usb_cfg pointer warning which is also
an error - src/soc/intel/meteorlake/fsp_params.c: error: 'usb_cfg' may
be used uninitialized in this function [-Werror=maybe-uninitialized]
BUG=None
TEST=./util/abuild/abuild for GOOGLE_HATCH, GOOGLE_VOLTEER, GOOGLE_KARIS
Change-Id: I169b6d3a979c4db78e7c0932a126d8b0a9306da7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85026
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch introduces an API to check whether CSE is booting from
the RW slot.
This information can be used to determine if a CSE firmware update is
pending, which would help to optimize the boot flow by knowing if any
reset is expected due to CSE sync.
TEST=Able to build google/brox.
Change-Id: I1a63ae9992d83b439a0f995d599ee475f7abd75b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch introduces support for storing the MRC cache based on the
MRC version for RPL platforms. This patch selects the
MRC_CACHE_USING_MRC_VERSION option when client SOC_INTEL_RAPTORLAKE is
chosen.
BUG=b:281846937
TEST=Able to build and boot google/brox and verify MRC version in CBMEM.
Change-Id: I8adf519c7f27b30d69c19f1c37cf410ac8ae54db
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
A following patch that adds some support for reading the serial flash
discoverable parameters (SFDP) data structures needs to send more than
just the one command byte that 'spi_flash_cmd' supports. To be able to
do this, introduce the 'spi_flash_cmd_multi' function which supports
sending multiple bytes before reading back some bytes. The prototype is
added to drivers/spi/spi_flash_internal.h since only other files in the
same directory are supposed to be using that function.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1f3872463249240c0a32e2825e4302894e856b2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84789
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Call the PSP RPMC NVRAM 'PSP RPMC NVRAM' instead of 'PSP NVRAM' in the
debug console output to not be misleading, since the RPMC feature uses
the 'PSP_RPMC_NVRAM' fmap section and not the 'PSP_NVRAM' fmap section.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie89dfcfe4b8780f422c222477bb627e03bd3662d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
- Boots Linux 6.11 (Debian)
- GRUB and SeaBIOS payloads work
- SMSC SCH5553 SIO/EC
+ Serial port works
+ PWM fan control works
- Realtek Gigabit LAN works
- WiFi slot works
- NVMe SSD slot works
- Extra: LPSS UART0
+ Stock FW sets undocumented power gating bit, RTC battery needs to
be pulled for it to work.
+ Signals exposed on test points on the back of the board.
FIXME: add documentation about this
- Needs 'deguard' to bypass BootGuard
+ See https://review.coreboot.org/admin/repos/deguard,general
- Audio works
- All USB ports work
- Currently limited to the Micro form factor, but others are very
similar
- HDA verbs and VBT by Leah Rowe
Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82053
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
acpigen_write_PRT_pre_routed writes _PRT covering all direct
subordinate child devices based on interrupt line/pin info from
their PCI configuration spaces. It is required that IRQ routing
and PCI configuration space update to be done ahead of time.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ic54888f76d2ec9804442bec5aec54267d9a16d7c
Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82253
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Rather than using a static array size for the `offset` variable, use a
pointer named `offsets` that points to a dynamically allocated array. A
separate variable called `offset_size` stores the size of this array.
TEST=emerge-corsola coreboot && emerge-geralt coreboot
Change-Id: I4b89c27fd693ee08e670c1a9ab4cbdbec220bee7
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
