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soc/intel/pantherlake: Update power limits config

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This updates power_limits_config for Panther Lake U and H.

Source:
  Intel PTL PDG 813278
  Intel PTL FSP Power limit profiles table

BUG=b:357011633
TEST=Build fatcat and boot with Panther Lake SoC and RVP.

Change-Id: I1b9276af7f1e30b1cda3d8c016524fd6397fa4b2
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This commit is contained in:
Jamie Ryu 2024-11-05 12:02:26 -08:00 • committed by Subrata Banik
commit 7e0c771c50
2 changed files with 9 additions and 9 deletions
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6
src/soc/intel/pantherlake/chip.h
View file

@ -65,9 +65,9 @@ static const struct {
} cpuid_to_ptl[] = {
{ PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W },
{ PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W },
{ PCI_DID_INTEL_PTL_H_ID_2, PTL_H_3_CORE, TDP_45W },
{ PCI_DID_INTEL_PTL_H_ID_3, PTL_H_1_CORE, TDP_25W },
{ PCI_DID_INTEL_PTL_H_ID_4, PTL_H_1_CORE, TDP_25W },
{ PCI_DID_INTEL_PTL_H_ID_2, PTL_H_1_CORE, TDP_25W },
{ PCI_DID_INTEL_PTL_H_ID_3, PTL_H_2_CORE, TDP_25W },
{ PCI_DID_INTEL_PTL_H_ID_4, PTL_H_2_CORE, TDP_25W },
};
/* Types of display ports */

12
src/soc/intel/pantherlake/chipset.cb
View file

@ -4,20 +4,20 @@ chip soc/intel/pantherlake
register "power_limits_config[PTL_U_1_CORE]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 54,
.tdp_pl4 = 142,
.tdp_pl2_override = 55,
.tdp_pl4 = 152,
}"
register "power_limits_config[PTL_H_1_CORE]" = "{
.tdp_pl1_override = 25,
.tdp_pl2_override = 64,
.tdp_pl4 = 154,
.tdp_pl2_override = 95,
.tdp_pl4 = 239,
}"
register "power_limits_config[PTL_H_2_CORE]" = "{
.tdp_pl1_override = 25,
.tdp_pl2_override = 80,
.tdp_pl4 = 240,
.tdp_pl2_override = 64,
.tdp_pl4 = 154,
}"
# NOTE: if any variant wants to override this value, use the same format