soc/intel/pantherlake: Add config option to limit DRAM frequency

This patch adds a new config option to limit the maximum DRAM
frequency for Pantherlake platforms.

The mainboard code should try to set `max_dram_speed_mts` from
override device tree if required.

BUG=b:373394046
TEST=Able to build and boot google/fatcat.

Change-Id: Ic92947b2997c116ea8ed0abff4c6b3c2ca956c65
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85101
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>

src/soc/intel/pantherlake/chip.h

@@ -512,6 +512,8 @@ struct soc_intel_pantherlake_config {
 	 */
 	uint8_t slow_slew_rate_config[NUM_VR_DOMAINS];
 
+	uint16_t max_dram_speed_mts;
+
 };
 
 typedef struct soc_intel_pantherlake_config config_t;

src/soc/intel/pantherlake/romstage/fsp_params.c

@@ -74,6 +74,9 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
 			m_cfg->SaGvWpMask = SAGV_POINTS_0_1_2_3;
 	}
 
+	if (config->max_dram_speed_mts)
+		m_cfg->DdrFreqLimit = config->max_dram_speed_mts;
+
 	m_cfg->RMT = config->rmt;
 	m_cfg->MrcFastBoot = 1;
 }